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參數資料
| 型號： | W6690 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | ISDN S/T Interface Controller(ISDN S/T接口控制器) |
| 中文描述： | 綜合業務數字網的S / T接口控制器（綜合業務數字網S / T的接口控制器） |
| 文件頁數： | 54/76頁 |
| 文件大小： | 471K |
| 代理商： | W6690 |
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Preliminary W6690
- 54 -
SW56 Switch 56 Traffic
0: The data rate in B1 channel is 64 Kbps.
1: The data rate in B1 channel is 56 Kbps. The most significant bit in each octet is fixed at "1".
Note: In 56 Kbps mode, only transparent mode can be used.
FTS1
0 FIFO Threshold Select
These two bits determine the B1 channel receive and transmit FIFO's threshold setting. An interrupt is
generated when the number of received data or the number of transmitted data reaches the threshold
value.
FTS1
0
0
1
1
FTS0
0
1
0
1
THRESHOLD (BYTE)
32
Reserved
48
Not allowed
8.2.5 B1_ch Extended Interrupt Register
B1_EXIR
Read clear
Address 24H
Value after reset: 00 H
7
6
5
4
3
2
1
0
RMR
RME
RDOV
XFR
XDUN
RMR Receive Message Ready
At least a threshold lenth of data has been stored in the B1_RFIFO.
RME Receive Message End
Used in transparent mode only. The last block of a frame has been received. The frame length can
be found in B1_RBCH + B1_RBCL registers. The number of data available in the B1_RFIFO equals
frame lenth modulus threshold. The result of CRC check is indicated by B1_STAR: CRCE bit.
When the number of last block of a frame equals the threshold, only RME interrupt is generated.
RDOV Receive Data Overflow
Data overflow occurs in the receive FIFO. The incoming data will overwrite the data in the receive
FIFO.
XFR Transmit FIFO Ready
This interrupt indicates that a threshold length of data can be written into the B1_XFIFO.
XDUN Transmit Data Underrun
This interrupt occurs when the B1_XFIFO has run out of data. In this case, the W6690 will
automatically reset the transmitter and send the inter frame time fill pattern on B channel. The
software must wait until transmit FIFO ready condition (via XFR interrupt or XFA bit), re-write data,
and issue XMS command to re-transmit the data.
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