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參數(shù)資料
| 型號： | W6690 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | ISDN S/T Interface Controller(ISDN S/T接口控制器) |
| 中文描述： | 綜合業(yè)務(wù)數(shù)字網(wǎng)的S / T接口控制器（綜合業(yè)務(wù)數(shù)字網(wǎng)S / T的接口控制器） |
| 文件頁數(shù)： | 9/76頁 |
| 文件大小： | 471K |
| 代理商： | W6690 |
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Preliminary W6690
Publication Release Date: March 1998
- 9 -
Revision A1
4. Pin Description, continued
PIN NAME PLCC-68 QFP-100
IOWC*/RW*
23
TYPE
I
DESCRIPTIONS
20
PNP ISA mode: ISA bus I/O write signal
ISA mode: ISA bus I/O write signal
Intel microcontroller mode: Write signal
Motorola microcontroller mode: Read/write. A "1"
identifies a read operation, a "0" identifies a write
operation.
O,4 mA PNP ISA mode: ISA bus No Wait signal. Used to
shorten a I/O access cycle. Normally, a 8-bit ISA I/O
slave cycle spends 6 clock time. The cycle can be
reduced to 3 clocks when NOWS* is used. NOWS* is
sampled on each falling edge of clock during the time
that the ISA command signal is asserted. The cycle
ends when NOWS* is sampled LOW.
ISA mode: Same as in PNP ISA mode.
Intel & Motorola microcontroller mode: Not used.
OD
PNP ISA mode: IRQ3
7, 9
12, 14
15 are ISA bus
interrupt request signals. For the selected IRQ pin, it is
high impedance when no interrupt and is driven to LOW
for more than 130 nS when interrupt occurs. For other
unselected pins, they are open drain.
ISA mode: Only IRQ3/IRQ* is used as the interrupt
request signal. It is high impedance when no interrupt
occurs and is driven to LOW for more than 130 nS when
interrupt occurs.
Intel & Motorola microcontroller mode: Only IRQ3/IRQ*
is used as the interrupt request signal. It is active LOW,
level triggered. It is open drain when no interrupt occurs
and is driven to LOW when interrupt occurs.
NOWS*
31
36
IRQ3/IRQ*
IRQ4
IRQ5
IRQ6
IRQ7
IRQ9
IRQ10
IRQ11
IRQ12
IRQ14
IRQ15
XTAL1
6
5
4
3
2
25
68
67
66
64
65
50
96
95
94
93
92
22
90
89
88
86
87
64
I
Connection for crystal input or oscillator clock input. The
clock frequency is 7.68 Mhz
±
100 ppm.
O, 4 mA Connection for crystal output. Left unconnected if
oscillator clock is used.
I
S/T bus receiver input (negative)
I
S/T bus receiver input (positive)
O
S/T bus transmitter output (positive)
O
S/T bus transmitter output (negative)
O, 4 mA PCM port 1 frame synchronization signal of 8 KHz
O, 4 mA PCM port 2 frame synchronization signal of 8 KHz
XTAL2
51
65
SR1
SR2
SX1
SX2
PFCK1
PFCK2
43
44
46
47
55
49
48
58
60
61
69
63
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