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參數資料
| 型號： | W6690 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | ISDN S/T Interface Controller(ISDN S/T接口控制器) |
| 中文描述： | 綜合業務數字網的S / T接口控制器（綜合業務數字網S / T的接口控制器） |
| 文件頁數： | 33/76頁 |
| 文件大小： | 471K |
| 代理商： | W6690 |
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Preliminary W6690
Publication Release Date: March 1998
- 33 -
Revision A1
micro-processor can read out a threshold length of data from receive FIFO at RMR interrupt, or all
the data in receive FIFO at RME interrupt. At each RMR/ RME interrupt, micro-processor must issue
a Receive Message Acknowledgement (RACK) command to explicitly acknowledge the interrupt.
The micro-processor reaction time for RMR/RME interrupt depends on the FIFO threshold setting and
B channel data rate. For example, it is 4 mS if the FIFO threshold is 32 and the B channel data rate is
64 Kbps.
If the micro-processor is late in handling the interrupt, the incoming additional bytes will result in a
"data overflow" interrupt and status bit.
Extended transparent mode:
In this mode, all data received are stored in the receive FIFO without any modification. Every time up
to a threshold length of data has been stored in the FIFO, a Bn_RMR interrupt is generated.
In this mode, there is no RME interrupt.
The micro-processor must react to the RMR interrupt in time, otherwise a "data overflow" interrupt
and status bit will be generated.
7.7.3 Transmission of Frames in B Channel
A 64-byte FIFO is provided in the transmit direction. The FIFO threshold can be set at 32 or 48 bytes.
The transmitter and receiver use the same FIFO threshold setting.
The transmit operations differ in both modes:
Transparent mode:
In this mode, the following functions are performed by the transmitter automatically :
Flag generation
CRC generation
Zero bit insertion
The fields such as address, control and information are provided by the micro-processor and are
stored in transmit FIFO. To start the frame transmission, the micro-processor issues a XMS (Transmit
Message Start) command. The transmitter requests another block of data via XFR interrupt when no
more than a threshold length of data are left in the FIFO.The micro-processor then writes up to a
threshold length of data into the FIFO and activates the subsequent transmission of the frame by a
XMS command too. The micro-processor indicates the end of the frame transmission by issuing XME
(Transmit Message End) and XMS commands at the same time. The transmitter then transmits all the
data left in the transmit FIFO and appends the CRC and closing flag. After this, a XFR interrupt is
generated.
The inter-frame time fill pattern can be programmed to 1's or flags.
During the frame transmission, the micro-processor reaction time for the XFR interrupt depends on
the FIFO threshold setting and B channel data rate. For example, it is 4 mS if the FIFO threshold is
32 and the B channel data rate is 64 Kbps. If the micro-processor fails to responds within the given
reaction time, the transmit FIFO will be underrun. In this case, the W6690 will automatically reset the
transmitter and send the inter frame time fill pattern on B channel. The micro-processor is informed
about this via a Transmit Data Underrun interrupt (XDUN bit in Bn_EXIR register). The
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