
Preliminary W6690
- 2 -
8.1.3 D_ch command register D_CMDR Write Address 02H.....................................................................40
8.1.4 D_ch Mode Register D_MODE Read/Write Address 03H.................................................................41
8.1.5 D_ch Timer Register D_TIMR Read/Write Address 04H ..................................................................43
8.1.6 Interrupt Status Register ISTA Read-clear Address 05H ...............................................................43
8.1.7 Interrupt Mask Register IMASK R/W Address 06H...........................................................................44
8.1.8 D_ch Extended Interrupt Register D_EXIR Read Clear Address 07H................................................44
8.1.9 D_ch Extended Interrupt Mask Register D_EXIM Read/Write Address 08H......................................45
8.1.10 D_ch Status Register D_STAR Read Address 09H......................................................................45
8.1.11 D_ch Receive Status Register D_RSTA Read Address 0AH..........................................................46
8.1.12 D_ch SAPI Address Mask D_SAM Read/Write Address 0BH .......................................................46
8.1.13 D_ch SAPI1 Register D_SAP1 Read/Write Address 0CH...............................................................46
8.1.14 D_ch SAPI2 Register D_SAP2 Read/Write Address 0DH...............................................................47
8.1.15 D_ch TEI Address Mask D_TAM Read/Write Address 0EH...........................................................47
8.1.16 D_ch TEI1 Register D_TEI1 Read/Write Address 0FH..................................................................47
8.1.17 D_ch TEI2 Register D_TEI2 Read/Write Address 10H ..................................................................47
8.1.18 D_ch Receive Frame Byte Count High D_RBCH Read Address 11H.............................................47
8.1.19 D_ch Receive Frame Byte Count Low D_RBCL Read Address 12H ..............................................48
8.1.20 D_ch Control Register D_CTL Read/Write Address 15H................................................................48
8.1.21 Command/Indication Receive Register CIR Read Address 16H ....................................................49
8.1.22 Command/Indication Transmit Register CIX Write Address 17H...................................................49
8.1.23 S/Q Channel Receive Register SQR Read Address 18H..............................................................50
8.1.24 S/Q Channel Transmit Register SQX Write Address 19H.............................................................50
8.1.25 PCM Control Register PCTL Read/Write Address 1AH ...............................................................50
8.2. B1 HDLC controler..............................................................................................................................51
8.2.1 B1_ch receive FIFO B1_RFIFO Read Address 20H.......................................................................52
8.2.2 B1_ch transmit FIFO B1_XFIFO Write Address 21H ....................................................................52
8.2.3 B1_ch command register B1_CMDR Write Address 22H...............................................................52
8.2.4 B1_ch Mode Register B1_MODE Read/Write Address 23H.............................................................53
8.2.5 B1_ch Extended Interrupt Register B1_EXIR Read clear Address 24H.............................................54
8.2.6 B1_ch Extended Interrupt Mask Register B1_EXIM Read/Write Address 25H...........55
8.2.7 B1_ch Status Register B1_STAR Read Address 26H......................................................................55
8.2.8 B1_ch Address Mask Register 1 B1_ADM1 Read/Write Address 27H.............................................56
8.2.9 B1_ch Address Mask Register 2 B1_ADM2 Read/Write Address 28H.............................................56
8.2.10 B1_ch Address Register 1 B1_ADR1 Read/Write Address 29H.....................................................56
8.2.11 B1_ch Address Register 2 B1_ADR2 Read/Write Address 2AH ....................................................56
8.2.12 B1_ch Receive Frame Byte Count Low B1_RBCL Read Address 2BH ...........................................57
8.2.13 B1_ch Receive Frame Byte Count High B1_RBCH Read Address 2CH..........................................57
8.3. B2 HDLC controller..............................................................................................................................57