
Preliminary W6690
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The functions provided by W6690 are:
Multiframe synchronization: Synchronization is achived when the M bit pattern has been
correctly received during 20 consecutive frames starting from frame number 1.
Note: Criterion for multiframe synchronization is not defined in I.430 Recommendation.
S bits receive and detect: When synchronization is achieved, the four received S bits in
frames 1, 6, 11, 16 are stored as S1 to S4 in the SQR register respectively. A change in the
recived four bits (S1-4) is indicated by an interrupt (ISC in D_EXIR register and SCC in CIR
register).
Multiframe synchronization monitoring: Multiframe synchronization is constantly monitored.
The synchronization state is indicated by the MSYN bit in the SQR register.
Q bits transmit and F
A
mirroring: When multiframe synchronization is achived, the four bits
Q1-4 stored in the SQXR register are transmitted as the four Q bits (F
A
-bit position) in frames
1, 6, 11 and 16. Otherwise the F
A
bit transmitted is a mirror of the received F
A
-bit. At loss of
synchronization, the mirroring is resumed at the next F
A
-bit.
The multiframe synchronization can be disabled by setting MFD bit in the D_MODE register.
According to I.430 Recommendation, the S/Q channel can be used as operation and
maintenance signalling channel. At transmitter, a S/Q code for a message shall be repeated
at least six times or as many as necessary to obtain the desired response. At receiver, a
message shall be considered received only when the proper codes is received three
consecutive times.
Table 7.6 Multiframe structure in S/T interface
Frame Number
NT-to-TE
F
A
-bit position
NT-to-TE
M bit
NT-to-TE
S bit
TE-to-NT
F
A
-bit position
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
ONE
ZERO
ZERO
ZERO
ZERO
ONE
ZERO
ZERO
ZERO
ZERO
ONE
ZERO
ZERO
ZERO
ZERO
ONE
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
S1
ZERO
ZERO
ZERO
ZERO
S2
ZERO
ZERO
ZERO
ZERO
S3
ZERO
ZERO
ZERO
ZERO
Q1
ZERO
ZERO
ZERO
ZERO
Q2
ZERO
ZERO
ZERO
ZERO
Q3
ZERO
ZERO
ZERO
ZERO