国产精品成人VA在线观看-国产乱妇乱子视频在播放-国产日韩精品一区二区三区在线-国模精品一区二区三区

參數(shù)資料
型號(hào)： W6690
廠(chǎng)商： WINBOND ELECTRONICS CORP
英文描述： ISDN S/T Interface Controller(ISDN S/T接口控制器)
中文描述： 綜合業(yè)務(wù)數(shù)字網(wǎng)的S / T接口控制器（綜合業(yè)務(wù)數(shù)字網(wǎng)S / T的接口控制器）
文件頁(yè)數(shù)： 32/76頁(yè)
文件大?。?/td> 471K
代理商： W6690
Preliminary W6690
- 32 -
The inter-frame time fill pattern must be all 1's, according to ITU-T I.430.
Collisions which occur on the D channel of S interface will cause an D_EXIR: XCOL interrupt. A
XRST (Transmitter Reset) command must be issued and software must wait until transmit FIFO ready
(via XFR interrupt), re-write data, and issue XMS command to re-transmit the data.
7.7 B Channel HDLC Controller
There are two B channel HDLC controllers. Each B channel HDLC controller provides two operation
modes:
Transparent mode
characteristics:
* 2 byte address field
* Receive address comparison maskable bit-by-bit
* Data between opening flag and CRC (not included) stored in receive FIFO
* Flag generation/ deletion
* Frame Check Sequence generation/ check with CRC_ITU-T polynominal
* Zero bit insertion/ deletion
Extended transparent mode
characteristics:
* All data transmitted/received without modification
* No address comparison
* No flag generation/ detection
* No FCS generation/ check
* No bit stuffing
For PCM-HDLC connection, only extended transparent mode can be selected.
The data rate in B channel can be set at 64 Kbps or 56 Kbps by the B1_MODE (B2_MODE): SW56
bit.
7.7.1 Reception of Frames in B Channel
A 64-byte FIFO is provided in the receive direction. The receive FIFO threshold can be set at 48 or
32 bytes by the Bn_MODE register. If the number of received data reaches the threshold, a Receive
Message Ready (RMR) interrupt will be generated.
The operations for reception of frames differ in each mode:
Transparent mode: The received frame address is compared with the contents in receive address
registers. In addition, the comparisons can be selectively masked bit-by-bit via address mask
registers. Comparison is disabled when the corresponding mask bit is "1".
In addition, flag recognition, CRC check and zero bit deletion are also performed. The result of CRC
check is indicated in Bn_STAR: CRCE bit. The data between opening flag and CRC field (not
included) is stored in receive FIFO. Two interrupts are used for the reception of data. The RMR
interrupt in Bn_EXIR register indicates at least a threshold block of data have been put in the receive
FIFO. The RME interrupt in Bn_EXIR register indicates the end of frame has been received. The
相關(guān)PDF資料
PDF描述
W66910CD TE Mode ISDN S/T-Controller with Microprocessor Interface
W6691 ISDN S/T Interface Transceiver
W6691CD ISDN S/T Interface Transceiver
W6691CP ISDN S/T Interface Transceiver
W6692 PCI Bus ISDN S/T Interface Controller(PCI總線(xiàn)的ISDN S/T接口控制器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
W6690ASX-1 制造商:Magnecraft 功能描述:Relay SSR 280V AC-IN 90A 660V AC-OUT 4-Pin
W6690DSX-1 制造商:Magnecraft 功能描述:Relay SSR 16mA 32V DC-IN 90A 660V AC-OUT 4-Pin
W6691 制造商:WINBOND 制造商全稱(chēng):Winbond 功能描述:ISDN S/T Interface Transceiver
W66910 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:
W66910CD 制造商:WINBOND 制造商全稱(chēng):Winbond 功能描述:TE Mode ISDN S/T-Controller with Microprocessor Interface
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠(chǎng)商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*