- 您現在的位置：買賣IC網 > PDF目錄363893 > W6690 (WINBOND ELECTRONICS CORP) ISDN S/T Interface Controller(ISDN S/T接口控制器) PDF資料下載
參數資料
| 型號： | W6690 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | ISDN S/T Interface Controller(ISDN S/T接口控制器) |
| 中文描述： | 綜合業務數字網的S / T接口控制器（綜合業務數字網S / T的接口控制器） |
| 文件頁數： | 43/76頁 |
| 文件大小： | 471K |
| 代理商： | W6690 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁當前第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁
Preliminary W6690
Publication Release Date: March 1998
- 43 -
Revision A1
8.1.5 D_ch Timer Register
D_TIMR
Read/Write
Address 04H
Value after reset: FFH
7
6
5
4
3
2
1
0
CNT2
CNT1
CNT0
VAL4
VAL3
VAL2
VAL1
VAL0
CNT together with VAL determine the time period T2 after which a TEXP interrupt will be generated:
T2 = CNT * 2.048 s + T1 with T1 = (VAL +1) * 0.064 s
The timer is started by setting the STT bit in D_CMDR and will be stopped when a TEXP interrupt is
generated or the D_TIMR register is written.
Note: If CNT is set to 7, a TEXP interrupt is generated periodically at every expiration of T1.
This register can be read only after the timer has been started. The read value indicates the timer's
current count value. In case layer 1 is not activated, a C/I command "ECK" must be issued in addition
to the STT command to start the timer.
8.1.6 Interrupt Status RegisterISTA
Read-clear
Address 05H
Value after reset: 00H
7
6
5
4
3
2
1
0
D_RMR
D_RME
D_XFR
D_EXI
B1_EXI
B2_EXI
D_RMR D_ch Receive Message Ready
A 32-byte data is available in the D_RFIFO. The frame is not complete yet.
D_RME D_ch Receive Message End
The last part of a frame with length > 32 bytes or a whole frame with length
≤
32 bytes has been
received. The whole frame length is obtained from D_RBCH + D_RBCL registers. The length of data
in the D_RFIFO equals:
data length = RBC4-0 if RBC4-0
≠
0
data length = 32 if RBC4-0 = 0
D_XFR D_ch Transmit FIFO Ready
This bit indicates that the transmit FIFO is ready to accept data. Up to 32 bytes of data can be written
into the D_XFIFO.
An D_XFR interrupt is generated in the following cases:
after an XMS command, when
≥
32 bytes of XFIFO is empty
after an XMS together with an XME command is issued, when the whole frame has been
transmitted
after an XRST command
after hardware reset
相關PDF資料 |
PDF描述 |
|---|---|
| W66910CD | TE Mode ISDN S/T-Controller with Microprocessor Interface |
| W6691 | ISDN S/T Interface Transceiver |
| W6691CD | ISDN S/T Interface Transceiver |
| W6691CP | ISDN S/T Interface Transceiver |
| W6692 | PCI Bus ISDN S/T Interface Controller(PCI總線的ISDN S/T接口控制器) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| W6690ASX-1 | 制造商:Magnecraft 功能描述:Relay SSR 280V AC-IN 90A 660V AC-OUT 4-Pin |
| W6690DSX-1 | 制造商:Magnecraft 功能描述:Relay SSR 16mA 32V DC-IN 90A 660V AC-OUT 4-Pin |
| W6691 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:ISDN S/T Interface Transceiver |
| W66910 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| W66910CD | 制造商:WINBOND 制造商全稱:Winbond 功能描述:TE Mode ISDN S/T-Controller with Microprocessor Interface |
發布緊急采購，3分鐘左右您將得到回復。