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參數資料
| 型號： | W6690 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | ISDN S/T Interface Controller(ISDN S/T接口控制器) |
| 中文描述： | 綜合業務數字網的S / T接口控制器（綜合業務數字網S / T的接口控制器） |
| 文件頁數： | 48/76頁 |
| 文件大小： | 471K |
| 代理商： | W6690 |
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Preliminary W6690
- 48 -
VN1
0 Chip Version Number
This is the chip version number. It is read as 00B.
LOV Length Overflow
A "1" in this bit indicates
≥
4097 bytes are received and the frame is not yet complete. This bit is valid
only after an D_RME interrupt and remains valid until the frame is acknowledge via the RACK
command.
RBC12
8 Receive Byte Count
Four most significant bits of the total frame length. These bits are valid only after an D_RME interrupt
and remain valid until the frame is acknowledge via the RACK command.
8.1.19 D_ch Receive Frame Byte Count Low D_RBCL
Read
Address 12H
Value after reset: 00H
7
RBC7
6
5
4
3
2
1
0
RBC6
RBC5
RBC4
RBC3
RBC2
RBC1
RBC0
RBC7
0 Receive Byte Count
Eight least significant bits of the total frame length. Bits RBC4-0 also indicate the length of the data
currently available in D_RFIFO. These bits are valid only after an D_RME interrupt and remain valid
until the frame is acknowledged via the RACK command.
8.1.20 D_ch Control Register D_CTL Read/Write
Address 15H
Value after reset: 00H
7
6
5
4
3
2
1
0
WTT1
WTT2
SRST
TPS
OPS1
OPS0
WTT1, 2 Watchdog Timer Trigger 1, 2
When the watchdog timer has enabled (D_MODE: TEE = 1 and D_CTL:TPS = 1), the micro-
processor has to program the WTT1, 2 bits in the following sequences within 1024 mS to reset and
restart the timer. Otherwise, the timer will expire after 1024 mS and a WEXP interrupt together with a
125
μ
S reset pulse on TRST pin are generated:
SEQUENCE
1
2
WTT1
1
0
WTT2
0
1
Switching TPS bit from 0 to 1 or from 1 to 0 resets the watchdog timer.
SRST Software Reset
When this bit is set to "1", a software reset signal is activated. The effects of this reset signal are
equivalent to the hardware reset pin RESET, except that it does not reset the PNP controller.
This bit is not auto-clear, the software must write "0" to this bit to exit from the reset mode.
Note: When SRST = 1, the chip is in reset state. Read or write to any of the registers is inhibited at this
time. The SRST bit is write only.
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