
Preliminary W6690
Publication Release Date: March 1998
- 53 -
Revision A1
XRST Transmitter Reset
Setting this bit resets the B1_ch HDLC transmitter and clears the B1_XFIFO. The transmitter will send
inter frame time fill pattern on B channel. This command also results in a transmit FIFO ready
condition.
8.2.4 B1_ch Mode Register
B1_MODE
Read/Write
Address 23H
Value after reset: 00H
7
6
5
4
3
2
1
0
MMS
ITF
EPCM
BSW1
BSW0
SW56
FTS1
FTS0
MDS Message Mode Setting
Determines the message transfer modes of the B1_ch HDLC controller :
0: Transparent mode. In receive direction, address comparison is performed on each frame. The
frames with matched address are stored in B1_RFIFO. Flag deletion, CRC check and zero bit
deletion are performed. In transmit direction, the data is transmitted with flag insertion, zero bit
insertion and CRC generation.
1: Extended transparent mode. In receive direction, all data are received and stored in the
B1_RFIFO. In transmit direction, all data in the B1_XFIFO are transmitted without alteration.
ITF Inter-frame Time Fill
Defines the inter-frame time fill pattern in transparent mode.
0: Mark. The binary value "1" is transmitted.
1: Flag. This is a sequence of "01111110".
EPCM Enable PCM Transmit/Receive
0: Disable data transmit/ receive to/from PCM port. The frame synchronization clock is held LOW.
1: Enable data transmit/ receive to/from PCM port. The frame synchronization clock is active.
BSW1
0 B Channel Switching Select
These two bits determine the connection in B1 channel:
BSW1
0
0
1
1
BSW0
0
1
0
1
CONNECTION
layer 1
HDLC
layer 1
PCM
HDLC
PCM
layer 1
→
PCM, PCM
→
HDLC
Note: The connection with micro-controller is through HDLC controller. When HDLC connects with layer 1, either transparent or
extended transparent mode can be used. When connecting with PCM port, the EPCM bit must be set to enable PCM
function.