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參數(shù)資料
型號(hào)： W89C940
廠商： WINBOND ELECTRONICS CORP
英文描述： ELANC-PCI (TWISTED-PAIR ETHER-LAN CONTROLLER WITH PCI INTERFACE)
中文描述： ELANC -的PCI（雙絞線醚局域網(wǎng)控制器帶有PCI接口）
文件頁(yè)數(shù)： 12/61頁(yè)
文件大小： 353K
代理商： W89C940
W89C940
12
Link Integrity
During periods of inactivity, link pulses are generated and received by both MAUs at either end of the twisted
pair to ensure that the cable has not been broken or shorted. A positive, 100 nS Link Integrity signal is
generated by the Twisted Pair Transceiver and transmitted on the twisted pair cable every 13 ms during periods
of no transmission activity. The ELANC-PCI assumes a link-good state if it senses valid link pulse activity on
the Twisted Pair Transceiver receive circuit. If neither receive data nor a link pulse (positive or negative) is
detected within 105 mS, the ELANC-PCI enters link-fail state. When a link-fail condition occurs, four
consecutive positive link pulses (or eight negative link pulses) must be received before a link-good condition is
assumed.
LCE CORE ACCESS FUNCTION
LCE core access function (LCE: Lan Controller of Ethernet)
The LCE core of the ELANC-PCI can be accessed by programming the register of the LCE core. The ELANC-
PCI's register files are mapped into the lower 16 I/O spaces: iobase to iobase+0FH. Any read/write to the
ELANC-PCI's registers is an "IN"/"OUT" command to these addresses.
Addresses iobase+10H to iobase+17H are mapped to the I/O port for the system to access the contents of the
buffer memory. Remote DMA reads and writes correspond to "IN"/"OUT" commands to these addresses.
When addresses iobase+18H to +1FH are read a software reset will be issued to the core coprocessor and
released about 780nsec later, automatically.
The following table summarizes the I/O address mapping:
ADDRESS
REGISTER
OPERATION
iobase+00H - iobase+0FH
LCE core's registers
Slave register read/write
iobase+10H - iobase+17H
I/O Ports
Remote DMA read/write
iobase+18H - iobase+1FH
Reset
Software reset
The buffer memory map for LCE core memory address space is summarized in the following table:
NE2000 COMPATIBLE
0000H - 001FH
ID Registers
0020H - 00FFH
0100H - 3FFFH
Unused
4000H - 7FFFH
16K X 8 local memory
8000H - FFFFH
Unused
NODE ID
Each node in an Ethernet network has a unique six-byte ID. The node ID is mapped into the memory space of
the ELANC-PCI. The ELANC-PCI will load the node ID from the EEPROM after power on reset. The node I.D.
should be allocated in the first 3 words(with the address of 00H ~ 02H) of the EEPROM.
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