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參數(shù)資料
| 型號： | W89C940 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | ELANC-PCI (TWISTED-PAIR ETHER-LAN CONTROLLER WITH PCI INTERFACE) |
| 中文描述： | ELANC -的PCI（雙絞線醚局域網(wǎng)控制器帶有PCI接口） |
| 文件頁數(shù)： | 9/61頁 |
| 文件大小： | 353K |
| 代理商： | W89C940 |
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W89C940
9
FUNCTIONAL DESCRIPTION
IEEE 802.3 MAC FUNCTION
Core Coprocessor (SLCT) Operation
The SLCT core coprocessor has five major logic blocks that control Ethernet operations: the register files,
transmit logic, receive logic, FIFO logic, and DMA logic. The relationship between these blocks is depicted in
the following block diagram.
Register Files
The register files of the SLCT can be accessed in the same way as the configuration registers. The ELANC-PCI
should be in slave mode when the system accesses the register files. The command register (CR) determines
the page number of the register file, while the system address SA<0:3> selects one register address from 01H
to 0fH. The PCI IO read/write commands are used to activate the I/O operations. Refer to the W89C90 data
sheet for more detailed information on the registers.
DMA Interface Logic
The SLCT has two types of DMA operations, local DMA and remote DMA.
FIFO Logic
The SLCT has a 16-byte FIFO, which acts as an internal buffer to adjust transmission/reception speed
differences between DMAs. The FIFO has FIFO threshold pointers to determine the level at which it should
initiate a local DMA. The threshold levels are different for reception and transmission. The FIFO threshold
levels are defined in the DCR register.
The FIFO logic also provides a FIFO overrun and underrun signal for network management purposes. In a case
where the receive packets are flooding into the FIFO but the SLCT still does not have the bus authority, the
FIFO may be overrun. On the other hand, if a transmission begins before data are fed into the FIFO, it may be
underrun. Both cases result in a network error. These types of cases can be prevented by changing the values
of the FIFO thresholds.
PCI
Bus
Interface
DMA
Interface
Logic
16-byte
FIFO
Transmit
Logic
Receive
Logic
SNA
TX/RX
Logic
Register
Files
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