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參數資料
| 型號： | W89C940 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | ELANC-PCI (TWISTED-PAIR ETHER-LAN CONTROLLER WITH PCI INTERFACE) |
| 中文描述： | ELANC -的PCI（雙絞線醚局域網控制器帶有PCI接口） |
| 文件頁數： | 15/61頁 |
| 文件大小： | 353K |
| 代理商： | W89C940 |
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W89C940
15
CONFIGURATION PROGRAMMING FUNCTION
ELANC-PCI Mode Configuration Registers
MCR
A mode configuration register(MCR) is used to program the operation mode of the ELANC-PCI. The address is
page 0, 0AH. MCR can be updated by software. Reading this register is the same as reading a register in the
SLCT core coprocessor. Writing to these registers is done by first reading the register to be written to and then
using a slave write operation to update the configurations.
The content of MCR is as following table:
BIT
0
1
SYMBOL
PHY0
PHY1
DESCRIPTION
Physical Layer Interface:
These two bits select the type of physical interface which the ELANC-PCI
attached on. Both the thin Ehternet and thick Ethernet type use the AUI of
ELANC-PCI as the input/output interface. The other two UTP types,then, use
the TPI of ELANC-PCI as the input/output interface. The output and input pins
of AUI or TPI are idle, when the corresponding type is not selected.
PHY1 PHY0 Physical Interface Type
0 0 UTP (with 10BASE-T compatible receive squelch level)
0 1 Thin Ethernet
1 0 Thick Ethernet (AUI port)
1 1 UTP (with reduced receive squelch level)
Good Link Status:
A read operation on this bit will get the link test status. A "1" indicate that it is
link good and a "0" is link fail.
The GDLNK do not imply any information if the PHY0 and PHY1 is
programmed as Thin or Thick Ethernet.
Link Test Pulse enable:
The network media auto switching function, link integrity test function and the
link test pulse generation function will be enabled when LNKEN = "0".
Otherwise, all of these functions will be disabled when LNKEN = "1".
SRAM High/Low Speed Select:
2
GDLNK
3
LNKEN
4
SHLS
High speed SRAM with 20nsec access time is selected if SHLS =1. Low
speed SRAM with 70nsec access time is selected if SHLS =0.
BOOT PROM Size:
The size of the BOOT PROM is selected by BPS0, BPS1, and BPS2.
BPS2 BPS1 BPS0 SIZE
0 0 X No boot PROM
0 1 0 8K
0 1 1 16K
1 0 0 32K
1 0 1 64K
1 1 0 128K
1 1 1 256K
5
6
7
BPS0
BPS1
BPS2
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