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參數資料
| 型號： | W89C940 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | ELANC-PCI (TWISTED-PAIR ETHER-LAN CONTROLLER WITH PCI INTERFACE) |
| 中文描述： | ELANC -的PCI（雙絞線醚局域網控制器帶有PCI接口） |
| 文件頁數： | 29/61頁 |
| 文件大小： | 353K |
| 代理商： | W89C940 |
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W89C940
29
CLK
FRAME#
AD[31::0]
IRDY#
TRDY#
ADDRESS
BUS CMD
BE#'s
1
2
3
4
15
16
17
C/BE[3::0]#
0
18
19
STOP#
DEVSEL#
Because W89C940 don't support memory command in burst mode. When the host try to send memory
command in burst mode, the first data phase is completed. TRDY# and IRDY# are deasserted, but the FRAME#
is asserted for the next data phase. The device will assert STOP# to terminate the transaction. Data is not
transferred after STOP# is asserted. The host need to initiate another transaction for further data transfer. The
timing is shown above.
The Target-Abort type, as shown in the figure
1
0
CLK
FRAME#
AD[31::0]
IRDY#
TRDY#
ADDRESS
BUS CMD
BE#'s
2
3
4
5
6
7
C/BE[3::0]#
STOP#
DEVSEL#
8
9
The condition is the target requires the transaction to be terminated and does not want the transaction tried
again. As shown in the figure, the DEVSEL# is deasserted when STOP# is asserted. If there is a data needed to
be transferred, DEVSEL# must be asserted for one or more clock cycles and TRDY# must be deasserted before
target-abort can be signaled.
There are two cases that the device will initiate the target-abort. The first one is the addressing parity check
error cause internal SERR# asserted and the second one is the Byte Enable and addressing check error. If
addressing don't match the following table, the target doesn't transfer the data, but terminate with target abort.
AD1
0
0
1
AD0
0
1
0
C/BE3#
X
X
X
C/BE2#
X
X
0
C/BE1#
X
0
1
C/BE0#
0
1
1
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