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參數(shù)資料
型號(hào)： W89C940
廠商： WINBOND ELECTRONICS CORP
英文描述： ELANC-PCI (TWISTED-PAIR ETHER-LAN CONTROLLER WITH PCI INTERFACE)
中文描述： ELANC -的PCI（雙絞線(xiàn)醚局域網(wǎng)控制器帶有PCI接口）
文件頁(yè)數(shù)： 22/61頁(yè)
文件大?。?/td> 353K
代理商： W89C940
W89C940
22
The read data will be kept in the BFR after the reading process is completed. The content of BFR will not
changed except that the other write or read sequence is started or a write(BFR, address) operation is executed.
i.e. the data of BFR can be read out any time afterwards.
EEPROM Content
The format of EEPROM contents is as followings:
ADDRESS
HIGH BYTE
Bit 15 ~ Bit 8
Reserved
Reserved
Reserved
Reserved
MCR
Device I.D.(high byte)
Vendor I.D.(high byte)
MAX_LAT
57H
Reserved
Reserved
Reserved
Reserved
Ethernet Address 5
Ethernet Address 3
Ethernet Address 1
LOW BYTE
Bit 7 ~ Bit 0
Reserved
Reserved
Reserved
Reserved
Revision I.D.
Device I.D.(low byte)
Vendor I.D.(low byte)
MIN_GNT
57H
Reserved
Reserved
Reserved
Reserved
Ethernet Address 4
Ethernet Address 2
Ethernet Address 0
0FH
0EH
0DH
0CH
0BH
0AH
09H
08H
07H
06H
05H
04H
03H
02H
01H
00H
The 5757H located at 07H address is used for NE2000 compatibility. The ELANC-PCI will load this parameter
into its internal register file for NE2000 software compatibility.
EEPROM Load Timing
A system reset should allow at least 1usec for the W89C940 to decode the action as a reset. After reset signal,
the device start to read the EEPROM after 1usec. The read clock is sent by the W89C940 to the EEPROM.
Normally the period of the clock is 1.2usec. It will take about 14.4usec to read the 12 bytes of data from
EEPROM.
The reset timing is as shown below.
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