
W89C940
5
PCI INTERFACE
NAME
NUMBER
TYPE
DESCRIPTION
IRDY#
11
s/t/s
in
Initiator Ready:
Initiator Ready indicates the host's ability to complete the current data phase of
transaction. During a write cycle, IRDY# indicates that valid data is presented on
AD[31:00]. During a read cycle, it indicates the master is ready to accept the
data. The wait cycles are inserted till IRDY# and TRDY# are asserted at the
same cycle.
TRDY#
12
s/t/s
Target Ready:
Target Ready indicates the W89C940's ability to complete the current data phase
of transaction. During a read cycle, TRDY# indicates that valid data is presented
on AD[31:00]. During a write cycle, it indicates the W89C940 is ready to accept
the data. The wait cycles are inserted till both IRDY# and TRDY# are asserted at
the same cycle.
STOP#
14
s/t/s
STOP:
Stop indicates W89C940 is requesting the master to stop the current transaction.
IDSEL
98
in
Initialization Device Select:
IDSEL is used as a chip select during PCI configuration read and write
transaction.
DEVSEL#
13
s/t/s
Device Select:
DEVSEL# will be asserted when W89C940 decode the correct address.
INTA#
88
o/d
Interrupt Request:
INTA# is used to request an interrupt service. The interrupt signal can be
masked by the register of IMR( Interrupt Mask Register). INTA# status is kept at
ISR( Interrupt Status Register).
NETWORK INTERFACE
NAME
NUMBER
TYPE
DESCRIPTION
X1
X2
53
52
I/TTL
O/TTL
Crystal or Oscillator Input.
Crystal or oscillator input (X1) and output (X2) pin. If a crystal is used, it should
be connected directly to X1 and X2. If an oscillator is selected, X1 is the 20 MHz
input and X2 should be left floating.
TXP
TXN
75
74
O/AUI
AUI Transmit Output:
AUI differential output pair. The data transmitted by DTE will be sent through TXP
and TXN in a differential signal with manchest code format. A 270 ohm pull-down
resistor is required for each of TXP and TXN. TXP and TXN should be isolated
by a pulse transformer from directly connecting outside loop.