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參數資料
| 型號： | W89C940 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | ELANC-PCI (TWISTED-PAIR ETHER-LAN CONTROLLER WITH PCI INTERFACE) |
| 中文描述： | ELANC -的PCI（雙絞線醚局域網控制器帶有PCI接口） |
| 文件頁數： | 4/61頁 |
| 文件大小： | 353K |
| 代理商： | W89C940 |
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W89C940
4
PIN DESCRIPTION
PCI INTERFACE
NAME
NUMBER
TYPE
DESCRIPTION
CLK
29
in
Clock:
Bus clock from PCI bus. All of the PCI signals, except RST#, are synchronized by
rising edge of clock.
The allowable operating frequency of CLK for W89C940 is from 25MHz to 33MHz.
RST#
87
in
Reset:
Asynchronous reset signal from PCI bus.
AD[31:00]
AD31-
AD24
AD23
AD22-
AD16
AD15-AD8
AD7-AD0
89 - 96
99
2 - 8
19 - 26
33 - 40
t/s
Address and Data:
Bidirection bus for PCI address and data signals transaction. AD[31:00] is a time
division bus. Two phases are used to carry the address and data messages of PCI
bus. The address phase is the clock cycle in which FRAME# is aeerted.
AD[31:24] contains the most significant byte(MSB) and the AD[7:0] contain the least
significant byte(LSB) during the data phase.
The data written from host should be stable and valid when IRDY# is asserted. The
data driven by W89C940 will be stable and valid when TRDY# is asserted.
C/BE[3:0]#
C/BE3#
C/BE2#
C/BE1#
C/BE0#
97
9
18
27
t/s
in
Bus Command and Byte Enables:
C/BE[3:0]# define the type of bus command during the address phase and the byte
enables during the data phase of a transaction. There are 16 types of bus
command defined in PCI bus. Four bits of C/BE[3:0]# are used to decode the 16
types of bus command. The byte enable determine which byte lanes carry
meaningful data.
C/BE0# indicate the byte 0(AD[7:0]) is valid. C/BE1# indicate the byte 1(AD[15:8]) is
valid. C/BE2# indicate the byte 2(AD[23:16]) is valid. C/BE3# indicate the byte
3(AD[32:24]) is valid.
PAR
17
t/s
Parity:
Even parity across AD[31:0] and C_BE[3:0]B.
W89C940 will drive the PAR in read data phase. The host drives the PAR for
address phase and writes data phase. PAR is stable and valid one clock after the
address phase. PAR is stable and valid one clock after either IRDY# is asserted on a
write transaction or TRDY# is asserted on a read transaction. Once PAR is valid, it
remains valid until one clock after the completion of the current data phase.
FRAME#
10
s/t/s
in
Cycle Frame:
FRAME# is asserted by host to indicate the beginning of a bus transaction. When
FRAME# is deasserted, the transaction is in the final data phase.
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