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參數資料
| 型號： | W89C940 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | ELANC-PCI (TWISTED-PAIR ETHER-LAN CONTROLLER WITH PCI INTERFACE) |
| 中文描述： | ELANC -的PCI（雙絞線醚局域網控制器帶有PCI接口） |
| 文件頁數： | 18/61頁 |
| 文件大小： | 353K |
| 代理商： | W89C940 |
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W89C940
18
Status Register
Bit Location
15
Attribute
R/W
Description
This bit will be set "1" by W89C940 when it detects a parity error,
even if parity error handling is disabled(as controlled by bit 6 in the
command register). A "write 1" operation on this bit will clear this
bit. This bit will be set "0" after it is cleared.
This bit will be set "1" by W89C940 when it assert the internal
SERR#. A "write 1" operation on this bit will clear this bit. This bit
will be set "0" after it is cleared. This bit is read only for 100 pin
package and is fixed to "0".
The W89C940 do not support PCI bus master function. This bit is
fixed to "0".
The W89C940 do not support PCI bus master function. This bit is
fixed to "0".
This bit will be set "1" by W89C940 when it terminates a
transaction with target-abort. A "write 1" operation on this bit will
clear this bit. This bit will be set "0" after it is cleared.
The Bit-10 is fixed to "0" and Bit-9 is fixed to "1". It indicated that
the W89C940 assert the DEVSEL# with medium speed.
The W89C940 do not support PCI bus master function. This bit is
fixed to "0".
The W89C940 support fast back-to-back transaction.
All of these bits are fixed to "0" internally. And no specific function
are related to these bits.
14
R/W
13
R
12
R
11
R/W
10~9
R
8
R
7
R
R
6~0
There are two cases that the W89C940 will initiate the target-abort. The first one is the addressing parity check
error cause internal SERR# asserted but without STOP# signal and the second one is the byte enable and
address check error that the STOP# is asserted. If addressing don't match the following table, the target doesn't
transfer the data, but terminate with target abort.
AD1
0
0
1
1
AD0
0
1
0
1
C/BE3#
X
X
X
0
C/BE2#
X
X
0
1
C/BE1#
X
0
1
1
C/BE0#
0
1
1
1
Revision I.D. Register
The revision I.D. is chosen by the vendor. It specifies a device specific revision identifier. Zero is an acceptable
value. It can be viewed as a vendor defined extension to the Device I.D. The content of this register will be
updated after power on by the EEPROM load operation. The revision ID should be programmed into the 23th
byte of the EEPROM for power on auto loading.
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