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參數資料
| 型號： | W89C940 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | ELANC-PCI (TWISTED-PAIR ETHER-LAN CONTROLLER WITH PCI INTERFACE) |
| 中文描述： | ELANC -的PCI（雙絞線醚局域網控制器帶有PCI接口） |
| 文件頁數： | 19/61頁 |
| 文件大小： | 353K |
| 代理商： | W89C940 |
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W89C940
19
Class Code Register
The Class Code Register is read only. The code of 020000H indicates that the W89C940 is a Ethernet
controller.
Cache-Line-Size Register
The W89C940 do not support the Memory Write and Invalidate command. All bits of this register are fixed to
"0".
Latency-Timer Register
The W89C940 do not implement a writable latency timer. All bits of this register are fixed to "0".
Header-Type Register
The W89C940 is a single function device. The bit 7 of header type register is fixed to "0" and all of other bits of
this register are also fixed to "0".
BIST Register
The W89C940 do not support the built in self test function. It will always return "00H" for a reading operation.
I/O-Base-Address Register
Bit
31~24
R/W
FFH
23~16
R/W
FFH
15~8
R/W
FFH
7
6
5
4
R
0
3
R
0
2
R
0
1
R
0
0
R
1
Attribute
Initial Value
R/W
1
R/W
1
R/W
1
The bit 0 fixed to "1" indicates that W89C940 requires the I/O space of the system as its buffer for data transfer.
The bit 0 to bit 4 implemented as a read only field imply that W89C940 need a I/O space with a range of 32
bytes. The power-up software can determine how munch address space the device required by writing a value
of all 1's to the register and then reading the value back. The W89C940 will return 0's in all don't care address
bits(bit 0 ~ bit 4), effectively specifying the address required, if the IDSEL and the configuration command are
recognized. The I/O base address will be decided by the bit 5 to bit 31 of the I/O base address register. The
system software should write the base address(32 bits address) onto this register. The bit 0 to bit 4 will be
ignored by W89C940. The bit 5 to bit 31 will be used as a reference value of the address decoder of the
W89C940.
There are nine types of command decoded by C/BE[0:3]# during the address phase of a transaction. These
nine types of command are as the following table.
C/BE[3:0]#
0010
0011
0110
0111
1010
1011
1100
1110
1111
Command Type
I/O Read
I/O Write
Memory Read
Memory Write
Configuration Read
Configuration Write
Memory Read Multiple, this command will be decoded as the Memory Read command
Memory Read Line, this command will be decoded as the Memory Read command
Memory Write and Invalidate, this command will be decoded as the Memory Write command
The last three commands are used in cache memory access. The application of W89C940 do not support this
command.
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