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參數(shù)資料
| 型號： | W90210F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PA-RISC Embedded Micro-Controller(惠普PA-RISC結(jié)構(gòu)的32位嵌入式微控制器) |
| 中文描述： | 32-BIT, MROM, RISC MICROCONTROLLER, PQFP208 |
| 封裝： | PLASTIC, QFP-208 |
| 文件頁數(shù)： | 14/67頁 |
| 文件大小： | 297K |
| 代理商： | W90210F |
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W90210F
14
Version 1.4, 10/8/97
The above information is the exclusive intellectual property of Winbond Electronics Corp. and shall not be disclosed, distributed or reproduced without permssion fromWinbond.
R
Recovery counter enable. When 1, recovery counter traps occur if bit 0 of the recovery counter is a 1. This
bit also enables decrementing of the recovery counter.
Interrupt state collection enable. When 1, interruption state is collected.
Non-existent register bit.
Non-existent register bit.
External interruption, power failure interrupt, and low-priority machine check interruption unmask. When 1,
these interruptions are unmasked and can cause an interruption.
Figure 5.2 Processor Status Word
Q
P
D
I
5.2.4 Control registers
There are twenty-five control registers in W90210F, numbered CR0, and CR8 through CR31, which contain
system state information. Figure 5.3 shows the control registers. The access of CR 11, 16, 26, and 27 are described in
the following table (table 5.4). Those control registers not listed in table 5.4 are only accessible by code executing at the
most privileged level. Control registers 1 through 7 are reserved registers. The unused bits of the Coprocessor
Configuration Register are reserved bits. The unused bits of the Shift Amount Register are nonexistent bits. In Level
systems, CRs 8, 9, 12, 13, 17, and 20 are nonexistent registers.
0
CR 0
Recovery Counter
CR 1
reserved
CR 7
reserved
CR 8
Nonexistent registers
CR 9
Nonexistent registers
CR 10
reserved
CR 11
nonexistent
CR 12
Nonexistent registers
CR 13
Nonexistent registers
CR 14
Interruption Vector Address
CR 15
External Interrupt Enable Masks
CR 16
Interval Timer
CR 17
Nonexistent registers
CR 18
Interruption Instruction Address Offset Queue
CR 19
Interruption Instruction Register
CR 20
Nonexistent registers
CR 21
Interruption Offset Register
CR 22
Interruption Processor Status Word
CR 23
External Interrupt Request Register
CR 24
Temporary Registers
CR 31
Temporary Registers
Figure 5.3 Control registers
31
SCR (8 bits)
CCR (8 bits)
SAR (5)
reserved
Privilege level for the access
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