
W90210F
21
Version 1.4, 10/8/97
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5.6 Interruptions
Interruptions are anomalies that occur during instruction processing causing the flow control to be passed to an
interruption handling routine. The interruptions are categorized into four groups based on their priorities. Interruption
numbers in table 5.17 are the individual vector numbers that determine which interruption handler is invoked for each
interruption. The group numbers determine when the particular interruption will be processed during the course of
instruction execution. The order the interruptions are listed within each group determines the priority of simultaneous
interruptions(from highest to lowest).
Group
1
interruption number
1
2
3
4
5
30
8
9
10
11
12
13
31
22
23
24
25
Interruption
High-priority machine check
Power failure interrupt
Recovery counter trap
External interrupt
Low-priority machine check
Instruction debug trap
Illegal instruction trap
BREAK instruction trap
Privileged operation trap
Privileged register trap
Overflow trap
Conditional trap
Data debug trap
Assist emulation trap
Higher-privilege transfer trap
Lower-privilege transfer trap
Taken branch trap
Table 5.17 Interruption number
2
3
4
Interruption handler routine begins execution at the address given by:
Interruption Vector Address + (32*nterruption_number)
However, handler of HPMC will start at 'initial address + 4', where 'initial address is the first instruction address
issued by W90K after RESET. There are two initial address (determined by PA/486#) , X'000FFFF0 or X'EFFFFFF0.
HMPC handler will start from either X'000FFFF4 or X'EFFFFFF4. This arrangement is to ensure that HPMC handler will
start first at a ROM address that is more reliable than DRAM.