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參數資料
| 型號： | W90210F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PA-RISC Embedded Micro-Controller(惠普PA-RISC結構的32位嵌入式微控制器) |
| 中文描述： | 32-BIT, MROM, RISC MICROCONTROLLER, PQFP208 |
| 封裝： | PLASTIC, QFP-208 |
| 文件頁數： | 16/67頁 |
| 文件大小： | 297K |
| 代理商： | W90210F |
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W90210F
16
Version 1.4, 10/8/97
The above information is the exclusive intellectual property of Winbond Electronics Corp. and shall not be disclosed, distributed or reproduced without permssion fromWinbond.
The W90210F CPU core implements all the instructions specified in the PA-RISC Rev. 1.1 third edition.
W90210F executes these instructions with results that comply to the PA-RISC architecture. MMU related instructions
are executed by W90210F as defined in the PA-RISC architecture for a Level 0 processor. PA-RISC multimedia
extension 1.0 instruction set is also supported by W90210F. To speed up multimedia operations in some applications,
three additional instructions are defined through the diagnostic instructions. In addition to that, debug SFU is provided to
enhance the debug capability. The chip also implements DIAG instructions defined by Winbond for chip testing,
diagnostics, and programming the internal AIR (architecture invisible register). These DIAG instructions comply with the
PA-RISC DIAG instructions.
5.3.1 Implementation of Level 0 instructions
In the Level 0 processor implementation, the S-fields of all instructions are ignored and have no effect on the
device functions. The following instructions for TLB handling are executed as null instructions, as specified in the
architecture reference manual:
Instruction
Function
PDTLB
Purge data TLB
PITLB
Purge instruction TLB
PDTLBE
Purge data TLB entry
PITLBE
Purge instruction TLB entry
IDTLBA
Insert data TLB address
IITLBA
Insert instruction TLB address
IDTLBP
Insert data TLB protection
IITLBP
Insert instruction TLB protection
Table 5.7 Instructions executed as null instructions
Table 5.8 lists the differences in instruction execution results in a Level 0 processor.
Instruction
Description
LPA
Load physical address
LCI
Load coherence index
LDWAX
Load word absolute index
LDWAS
Load word absolute short
STWAS
Store word absolute short
GATE
Gateway
BV
Branch vectored
BE
BLE
Branch and link external
RFI
RFIR
Return from interrupt and restore
LDSID
Load space identifier
MTSP
Move to space register
MTCTL
Move to control register
Difference
Undefined instruction
Undefined instruction
Same as LDWX if priv=0
Same as LDWS if priv=0
Same was STWS if priv=0
Always promote priv to 0
Demote priv to any non zero value
Demote priv to any non zero value, IASQ is nonexistent
Branch external
Return from interrupt
IASQ is nonexistent
0 is written into specified GR
Executed as null instruction
Executed as null instruction if target is 8,9,12,13,17 or
20
is written into specified GR
0 is written into specified GR if source is 8,9,12,13,17 or
20
Always set target GR to 1
Always set target GR to 1
Always set target GR to 1
Always set target GR to 1
Table 5.8 Summary of Level 0 instruction differences
MFSP
MFCTL
Move from space register
Move from control register
PROBER
PROBERI
PROBEW
PROBEWI
Probe read access
Probe read access immediate
Probe write access
Probe write access immediate
5.3.2 Implementation of cache-related instructions
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