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參數資料
| 型號： | W90210F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PA-RISC Embedded Micro-Controller(惠普PA-RISC結構的32位嵌入式微控制器) |
| 中文描述： | 32-BIT, MROM, RISC MICROCONTROLLER, PQFP208 |
| 封裝： | PLASTIC, QFP-208 |
| 文件頁數： | 26/67頁 |
| 文件大小： | 297K |
| 代理商： | W90210F |
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W90210F
26
Version 1.4, 10/8/97
The above information is the exclusive intellectual property of Winbond Electronics Corp. and shall not be disclosed, distributed or reproduced without permssion fromWinbond.
8. Megacells Description
8.1 DRAMController & ROMController
8.1.1 DRAMcontroller
The DRAM controller supports four separate banks of dynamic memory. Either X9 or X36 SIMMs are
supported. CAS#-before-RAS# refresh cycles are performed periodically, as determined by the refresh timer. The
DRAM controller must arbitrate between access requests and refresh requests. EDO fast page mode and parity check
are also supported.
Bus
Interface
to
CPU core
Refresh Timer
RAS#[4]
CAS#[4]
MA[12]
DRAM Configuration
Register
DRAM Type Register
DRAM Timing
Register
Bank Base Address
Registers
WE#
MD[32]
CPU interface
Figure 8.1 DRAMcontroller block diagram
For each bank of DRAM, there will be registers to specify the bank base address and the bank DRAM type:
Bank Base Address Register.
Bank Type Register.
DRAM Type Register is used to program the DRAM type of each bank.
Bank
0
Bank
1
Bank
2
Bank
3
DRAM Type
DRAM Type Register
00 : 256K DRAM cell
01 : 1M DRAM cell
10 : 4M DRAM cell
11 : 16M DRAM cell
0 1 2 3 4 5 6 7
Figure 8.2 DRAMType register programmng
DRAM Timing Register is used to program DRAM timing parameters:
2ah
[6:7] Write cycle RAS# to CAS# delay.
[4:5] Read cycle RAS# to CAS# delay
[3] Write cycle CAS# pulse width.
[2] CAS# precharge time.
[0:1] RAS# precharge time.
2bh
[6:7] Read cycle. CAS# pulse width.
[5] Refresh cycle. CAS# active to RAS# active delay.
[3:4] Refresh cycle. RAS# active to CAS# inactive delay.
[1:2] Refresh cycle. RAS# active pulse width.
[0] Parity check enable.
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