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參數資料
| 型號： | W90210F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PA-RISC Embedded Micro-Controller(惠普PA-RISC結構的32位嵌入式微控制器) |
| 中文描述： | 32-BIT, MROM, RISC MICROCONTROLLER, PQFP208 |
| 封裝： | PLASTIC, QFP-208 |
| 文件頁數： | 36/67頁 |
| 文件大小： | 297K |
| 代理商： | W90210F |
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W90210F
36
Version 1.4, 10/8/97
The above information is the exclusive intellectual property of Winbond Electronics Corp. and shall not be disclosed, distributed or reproduced without permssion fromWinbond.
8.5 Parallel Port
The parallel port megacell implements the IEEE 1284 parallel port. The IEEE 1284 standard provides for high
speed bi-directional communication between the PC and an external peripheral.
The parallel port defines 5 modes of data transfer. Each mode provides a method of transfering data in either
the forward direction, reverse direction, or bi-directional data transfer. The defined modes are:
Standard parallel port mode
PS/2 parallel port mode
Parallel port FIFO mode
ECP parallel port mode
Centronix Peripheral mode (Vendor specified mode)
Other modes defined in the IEEE 1284 standard like test mode and configuration mode are also supported.
8.5.1 ECP Register Description
1. Data Register (offset 378) R/W
0
7
This is the standard parallel port data register. Writing to this register in Standard mode shall drive data to the
parallel port data lines. In all other modes the drivers may be tri-stated by setting the direction bit in the dcr
register. Read to this register return the value on the data lines.
Standard mode:
write data_reg: cpu_data[0:7]
→
data_reg[0:7]
→
PAD_ED[0:7]
read data_reg: data_reg[0:7]
→
cpu_data
PS/2 mode, forward:
write data_reg: cpu_daa
→
data_reg
→
PAD_ED
read data_reg: data_reg
→
cpu_data
PS/2 mode, reverse:
write data_reg: cpu_data
→
data_reg
read data_reg: PAD_ED
→
cpu_data
Centronix Peripheral mode:
read data_reg: PAD_ED
→
cpu_data
Other mode:
write data_reg: cpu_data[0:7]
→
data_reg[0:7]
read data_reg: undefined
2. DSR register (offset 379) Read only
0
7
This read-only register reflects the inputs on the parallel port interface.
Bit [0]- nBusy:
inverted parallel port
Busy
signal
Bit [1]- nAck:
parallel port
nAck
signal
Bit [2]- PError:
parallel port
PError
signal
Bit [3]- Select:
parallel port
Select
signal
Bit [4]- nFault:
parallel port
nFault
signal
Bit [5:7]- reserved
3. DCR register (offset 37a) R/W
0
7
This register directly controls several output signals as well as enabling some functions. The drivers for nStrobe,
nAutoFd, nInit, and nSelectIn are open-collector in standard mode.
Bit [0:1]- reserved
Bit [2]- Direction
0: forward (default)
Drivers are enabled.
1: reserved
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