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參數(shù)資料
| 型號(hào)： | W90210F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PA-RISC Embedded Micro-Controller(惠普PA-RISC結(jié)構(gòu)的32位嵌入式微控制器) |
| 中文描述： | 32-BIT, MROM, RISC MICROCONTROLLER, PQFP208 |
| 封裝： | PLASTIC, QFP-208 |
| 文件頁數(shù)： | 19/67頁 |
| 文件大小： | 297K |
| 代理商： | W90210F |
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W90210F
19
Version 1.4, 10/8/97
The above information is the exclusive intellectual property of Winbond Electronics Corp. and shall not be disclosed, distributed or reproduced without permssion fromWinbond.
5.4. Debug Special Function Unit
The debug special function unit is an optional, architected SFU which provides hardware assistance for
software debugging using breakpoints. The debug SFU is currently provided in the W90210F CPU core. The debug
SFU supports two sets of registers for both data breakpoints and instruction breakpoints.
For the instruction debug trap, the trapping address is stored in the interruption instruction address offset
queue (IIAOQ). For the data debug trap, the trapping address is stored in the interruption offset register (IOR).
The e bit in each IBAMR determines whether this instruction breakpoint is enabled. If the e bit is 1, any attempt
to execute an instruction (including nullified instructions) at an address matching the corresponding IBAOR will cause an
instruction debug trap. If the e bit is 0, that instruction breakpoint is disabled.
Instruction Breakpoint Address Offset Register (IBAOR0, IBAOR1)
:
0
31
address offset
IBAOR
Instruction Breakpoint Address Mask Register (IBAMR0, IBAMR1)
:
0
1
31
mask
rv
e
7 8
IBAMR
Data Breakpoint Address Offset Register (DBAOR0, DBAOR1)
:
0
31
address offset
DBAOR
Data Breakpoint Address Mask Register (DBAMR0, DBAMR1)
:
0
1 2
31
mask
7 8
r w
rv
DBAMR
Figure 5.12 Debug SFU registers
The r and w bits in each DBAMR determine the type of access this data breakpoint is enabled for. If the r bit is
1, any non-nullified load or semaphore instruction to an address matching the corresponding DBAOR will cause a data
debug trap. If the w bit is 1, any non-nullified store or semaphore instruction or cache purge operation to an address
matching the corresponding DBAOR will cause a data debug trap. If the r and w bits are both 0, the data breakpoint is
disabled.
For the control of the debug SFU, three bits are added to the PSW register.
Debug Trap Enable Bit (G)
: Bit 25 of the PSW is defined as the G-bit- the debug trap enable bit. When the G-bit is
1, the data debug trap and instruction debug trap are enabled; when 0, the traps are disabled. The G-bit is set to 0 on
interruptions.
Data Debug Trap disable Bit (Y)
: Bit 0 of the PSW is defined as the Y-bit. The Y-bit is set to 0 after the execution of
each instruction, except for RFI and RFIR instructions which may set it to 1. When 1, data debug traps are disabled.
Instruction Debug Trap disable Bit (Z)
: Bit 1 of the PSW is defined as the Z-bit. The Z-bit is set to 0 after the
execution of each instruction, except for RFI and RFIR instructions which may set it to 1. When 1, instruction debug
traps are disabled.
In addition, CCR bits 16- 23 are used as enable/disable bits for SFUs 0- 7. The debug SFU will use bit 17.
When bit 17 is enabled, the SFU #1 instructions will operate normally, but when disabled, all SFU #1 instructions will
take an assist emulation trap.
Two new exceptions are added to the architecture- one for instruction debugging and one for data debugging.
Instruction Debug Trap (30)
: Interruption #30 is now defined as the instruction debug trap. This trap belongs to
group 3.
Data Debug Trap (31)
: Interruption #31 is defined as the data debug trap. This trap belongs to group3.
Following instructions are added for the debug SFU.
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