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參數資料
| 型號： | W90210F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PA-RISC Embedded Micro-Controller(惠普PA-RISC結構的32位嵌入式微控制器) |
| 中文描述： | 32-BIT, MROM, RISC MICROCONTROLLER, PQFP208 |
| 封裝： | PLASTIC, QFP-208 |
| 文件頁數： | 15/67頁 |
| 文件大小： | 297K |
| 代理商： | W90210F |
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W90210F
15
Version 1.4, 10/8/97
The above information is the exclusive intellectual property of Winbond Electronics Corp. and shall not be disclosed, distributed or reproduced without permssion fromWinbond.
CR 11
CR 16
read/write at any privilege level
PSW 'S'=0: read/write by any privilege level
PSW 'S'=1: read/write by privileged software
readable at any privilege level
writable at the most privileged level
Accessible only at most privileged level
Table 5.4 Access of control registers
CR 26, 27
Others
5.2.5 W90210F External Interrupt Request register (EIRR; CR23)
EI[0:4]
External
Interrupt
00000
Timer_Int
10000
01000
11000
00100
10100
01100
11100
00010
Parallel_Int
10010
Serial_Int
01010
DMA_Int
11010
12 - 31
-
Bit
Number
0
1
2
3
4
5
6
7
8
9
10
11
Description
Interval Timer (CR16) interrupt request
-
-
Serial
INTA
INTB
INTC
INTD
Serial port interrupt request from COM2
PCI bus INTA# interrupt request
PCI bus INTB# interrupt request
PCI bus INTC# interrupt request
PCI bus INTD# interrupt request
Parallel port interrupt request
Serial port interrupt request from COM1
DMA interrupt request
Timer/Counter interrupt request
Reserved
Table 5.5 External Interrupt Request Register
TC_Int
-
5.2.6 AIRs (Architecture Invisible Registers)
There are eight AIRs in the W90210F. AIR[0] controls the internal cache configuration, burst mode, and default
endian. AIR[0] is documented in this data sheet. AIR[1] and AIR[2] are reserved for chip testing by Winbond, and their
functions will not be disclosed to users. Attempting to access these two registers may cause programs to be executed
with unpredictable results. Memory configuration registers are used for programming the configuration of W90210F
memory space. AIR[7] is the PCO register, this AIR can only be accessed through the JTAG ICE interface.
AIR[0]
Internal configuration register
AIR[1]
PSW register
AIR[2]
TMR register
AIR[3]
Memory configuration register 1
AIR[4]
Memory configuration register 2
AIR[5]
Memory configuration register 3
AIR[6]
Memory configuration register 4
AIR[7]
PCO register (program counter)
Table 5.6 W90210F CPU core AIRs
Important:
Enabling or disabling the internal I-cache with MTAIR[0] will invalidate all I-cache entries automatically.
Enabling the internal D-cache with MTAIR[0] will invalidate all cache entries without dirty data entries being written back.
Disabling the D-cache, however, will not invalidate cache entries.
Disabling the internal D-cache with MTAIR[0] will cause dirty data to be left in the D-Cache and not
automatically written into memory. When a program references the dirty data location, stale data in memory will be
returned. To prevent this, a cache invalidation routine should be performed before the internal D-cache is disabled. The
invalidation routine must flush all cache entries one by one. This will invalidate the cache and also write back any dirty
data.
AIR[1] and AIR[2] are reserved registers and should never be written to or read from them. Accessing these
registers will cause unpredictable result.
5.3 Implementation of the PA-RISC instructions
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