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參數資料
| 型號： | W90210F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PA-RISC Embedded Micro-Controller(惠普PA-RISC結構的32位嵌入式微控制器) |
| 中文描述： | 32-BIT, MROM, RISC MICROCONTROLLER, PQFP208 |
| 封裝： | PLASTIC, QFP-208 |
| 文件頁數： | 20/67頁 |
| 文件大小： | 297K |
| 代理商： | W90210F |
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W90210F
20
Version 1.4, 10/8/97
The above information is the exclusive intellectual property of Winbond Electronics Corp. and shall not be disclosed, distributed or reproduced without permssion fromWinbond.
Mnemonic
MTDBAO
MFDBAO
MTDBAM
MFDBAM
MTIBAO
MFIBAO
MTIBAM
MFIBAM
DEBUGID
Description
Move to data breakpoint address offset register
Move from data breakpoint address offset register
Move to data breakpoint address mask register
Move from data breakpoint address mask register
Move to instruction breakpoint address offset register
Move from instruction breakpoint address offset register
Move to instruction breakpoint address mask register
Move from instruction breakpoint address mask register
Debug SFU identify
Table 5.13 Debug SFU instructions
Operation
DBAOR[t]
←
GR[r]
GR[t]
←
DBAOR[r]
DBAMR[t]
←
GR[r]
GR[t]
←
DBAMR[r]
IBAOR[t]
←
GR[r]
GR[t]
←
IBAOR[r]
IBAMR[t]
←
GR[r]
GR[t]
←
IBAMR[r]
GR[t]
←
id number
5.5 Addressing and access control
The W90210F implements real mode addressing. The total addressable space for the W90210F is 4 GB.
Objects in the memory and I/O system are addressed using 32-bit absolute addresses. An absolute pointer is a 32-bit
unsigned integer whose value is the address of the lowest addressed byte of the operand it designates. The address
mapping is same as that specified by the PA-RISC architecture.
5.5.1 Memory and I/O space
X'00000000
Memory Address Space
X'EFFFFFFF
X'F0000000
I/O Address Space
X'FFFFFFFF
Figure 5.16 Memory and I/O addresses
Figure 5.16 shows the memory and I/O address space allocation.
Total memory address space available is (4 GB-256 MB). Total addressable I/O space is 256 MB.
Program address for I/O:
Fxxxxxxx
W90210F CPU core output address:
0xxxxxxx
5.5.2 RESET addresses
The initial instruction address after a hardware reset is not defined in the PA-RISC architecture. Two reset
addresses are provided for W90210F CPU core. W90210F CPU core will sample the input pin "PA/486#" at the trailing
edge of RESET to determine the initial instruction address. When PA/486# pin is low, the initial address will be
000FFFF0; when PA/486# is high, it will be EFFFFFF0. This pointer ensures that the program starts execution from
ROM space when used in an X86-compatible board. W90210F CPU core has an internal pull down resistor that will set
W90210F CPU to generate X86-like initial address if the PA/486# is left unconnected.
For W90210F, the reset address is always EFFFFFF0.
5.5.3 Access control
Every instruction is fetched and executed at one of four privilege levels (numbered 0,1 2, 3) with 0 being the
most privileged. The privilege level is kept in the bits 30 and 31 of the current instruction's address. Base relative branch
instructions (BV, BE and BLE) will demote privilege level to any non zero value, if it changes it. GATEWAY instruction
promotes the privilege level to 0. Other branch instructions have word offset only and will not change privilege level.
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