- 您現在的位置：買賣IC網 > PDF目錄363904 > W90210F (WINBOND ELECTRONICS CORP) PA-RISC Embedded Micro-Controller(惠普PA-RISC結構的32位嵌入式微控制器) PDF資料下載
參數資料
| 型號： | W90210F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PA-RISC Embedded Micro-Controller(惠普PA-RISC結構的32位嵌入式微控制器) |
| 中文描述： | 32-BIT, MROM, RISC MICROCONTROLLER, PQFP208 |
| 封裝： | PLASTIC, QFP-208 |
| 文件頁數： | 25/67頁 |
| 文件大小： | 297K |
| 代理商： | W90210F |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁當前第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁
W90210F
25
Version 1.4, 10/8/97
The above information is the exclusive intellectual property of Winbond Electronics Corp. and shall not be disclosed, distributed or reproduced without permssion fromWinbond.
needed for the program execution (i.e., a data dependency is encountered) or when a second miss cycle occurs before
the first miss cycle is serviced. The "hit under miss" scheme helps to minimize the D-cache miss penalty.
Separate byte write enables are provided for store instructions. This feature enables the W90210F to execute
store byte(s) instructions without read-modify-write operation.
7.2.1 Write-through Cache Support
Normally, the data cache is a write-back cache. Range for the write-through cache address space can be
defined in the AIR.
Write-through base register[0:15]: This register defines the base address of the write-through address range.
Write-through region size register: This register defines the size of the write-through address range:
000:
disable
001:
64K
010:
128K
(base address must be multiple of 128K)
011:
256K
(base address must be multiple of 256K)
100:
512K
(base address must be multiple of 512K)
101:
1M
(base address must be multiple of 1M)
110:
2M
(base address must be multiple of 2M)
111:
4M
(base address must be multiple of 4M)
Important:
User must flush the data cache before setting up these two registers.
7.3 Non-cacheable address space
User can define two non-cacheable regions with sizes ranging from 64K to 4M Byte. BIU can use these two
ranges to decide whether current bus cycle is cacheable or not.
Non-cacheable base address register: This register defines the base address of the non-cacheable address
range.
Non-cacheable region size register: This register defines the size of the non-cacheable address range:
000:
disable
001:
64K
010:
128K
(base address must be multiple of 128K)
011:
256K
(base address must be multiple of 256K)
100:
512K
(base address must be multiple of 512K)
101:
1M
(base address must be multiple of 1M)
110:
2M
(base address must be multiple of 2M)
111:
4M
(base address must be multiple of 4M)
The memory address space above 1MB, 2MB, 4MB, 8MB, 16MB, 64MB, 128MB or 256MB can also be turned
into a third non-cacheable region. This is defined by the system non-cacheable region register:
cacheable
0001:
above 1MB
0010:
above 2MB
0011:
above 4MB
0100:
above 8MB
0101:
above 16MB
0110:
above 32MB
0111:
above 64MB
1000:
above 128MB
1001:
above 256MB
0000:
all
相關PDF資料 |
PDF描述 |
|---|---|
| W90220F | PA-RISC Embedded Micro-Controller(惠普PA-RISC結構的32位嵌入式微控制器) |
| W90221F | PA-RISC Embedded Micro-Controller(惠普PA-RISC結構的32位嵌入式微控制器) |
| W91030B | Low Power CMOS IC For Caller indentification(用于通信中呼叫確認的低功耗CMOS集成電路芯片) |
| W91030 | Low Power CMOS IC For Caller indentification(用于通信中呼叫確認的低功耗CMOS集成電路芯片) |
| W91031 | LOW POWER CMOS INTERGRATED CIRCUIT |
相關代理商/技術參數 |
參數描述 |
|---|---|
| W902E31 | 制造商:Omron Corporation 功能描述: |
| W903B-28C | 制造商: 功能描述: 制造商:undefined 功能描述: |
| W903B48D | 制造商: 功能描述: 制造商:undefined 功能描述: |
| W905 | 制造商:LUMINIS 制造商全稱:LUMINIS 功能描述:Post top mount |
| W9050B016 | 制造商:Pulse Electronics Corporation 功能描述:1.13OD 1.6'' I-Pex to I-Pex Cable Assembly |
發布緊急采購，3分鐘左右您將得到回復。