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參數(shù)資料
型號(hào)： W90220F
廠商： WINBOND ELECTRONICS CORP
元件分類： 微控制器/微處理器
英文描述： PA-RISC Embedded Micro-Controller(惠普PA-RISC結(jié)構(gòu)的32位嵌入式微控制器)
中文描述： 32-BIT, 150 MHz, RISC PROCESSOR, PQFP208
封裝： PLASTIC, QFP-208
文件頁(yè)數(shù)： 10/79頁(yè)
文件大小： 501K
代理商： W90220F
W90220F
10
The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from
Version 0.84
Winbond.
RAS#[2:3]/
PREQ#[2:3]
I/O
14, 15
If MD[20] is pull down, these pins serve RAS signals for
external DRAM's bank 2 and 3.
If MD[20] is pull high, these pins serve as "PCI Request 2
and 3" indicate to the PCI arbiter that the masters desires
use of the bus
DRAM Column Address Strobes, Byte 0-3. These signals are
used to select the DRAM column address. A High-to-Low
transition on these signals causes the DRAM selected by
RAS#[0:3] to latch the column address and complete the
access.
DRAM Write Enable signal is used to write the selected
DRAM bank.
ROM Chip Selects, Banks 0-1. A low level on one of these
signals selects the memory devices in the corresponding
ROM bank.
If MD[20] is pull down, these pins serve ROM "Chip select"
for
bank 2 and 3.
If MD[20] is pull high, these pins serve as "PCI Grant 2 and
3" indicate to the PCI masters that access to the PCI bus has
been granted.
ROM Address Latch, ROM address are divided into two
portions, higher address bits and lower address bits, the
address will be put out on the MA bus in two consecutive
cycles. The ROMEN signal is used to latch the higher
address bits in the first ROM address cycle.
FLASH ROM write enable. This signal is used to write data
into the mrmory in a ROM bank (such as Flash ROM).
ROM output enable. This signal enables the selected ROM
Bank to drive the MD bus.
Memory controller Memory Address bus. For DRAM access,
MA[0:11] is the DRAM row address and the DRAM column
address. For ROM/FLASH ROM access, MA[0:11] is the
higher portion ROM space address bits in the first ROM
address cycle, and the lower portion ROM space address bits
after the first ROM address cycle. During DMA I/O cycles,
these pins also serve as DMA address bus. MA[0] is the
most significant bit (msb).
Memory controller Data bus bit 0-7 for both DRAM data and
ROM space data. Bit 0 is the most significant bit (msb).
Memory controller Data bus bit 8-15for both DRAM data and
ROM space data. During DMA cycles, these pins also serve
as DMA data bus bit 8-15 for 16-bit DMA transfering. Bit 8 is
the most significant bit (msb).
Memory controller Data bus bit 16-31 for both DRAM data
and ROM space data. Bit 16 is the most significant bit (msb).
CAS#[0:3]
O
197, 201-203
WE#
O
204
RCS#[0:1]
O
16, 17
RCS#[2:3]/
GNT#[2:3]
O
18, 19
ROMEN
O
22
ROMRW#
O
38
ROMOE#
O
39
MA[0:11]/
DA[0:11]
O
20-21, 23-25,
27-28, 32, 34-
37
MD[0:7]
I/O
157-164
MD[8:15]/
DD[8:15]
I/O
166, 168,
170-175
MD[16:31]
I/O
176-179,
181,182,184-
191,193,195
COM1 Serial Port Signal
SIN1
I
1
COM1 serial data input from the communication link (modem
or peripheral device).
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