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參數(shù)資料
| 型號(hào)： | W90220F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PA-RISC Embedded Micro-Controller(惠普PA-RISC結(jié)構(gòu)的32位嵌入式微控制器) |
| 中文描述： | 32-BIT, 150 MHz, RISC PROCESSOR, PQFP208 |
| 封裝： | PLASTIC, QFP-208 |
| 文件頁數(shù)： | 60/79頁 |
| 文件大?。?/td> | 501K |
| 代理商： | W90220F |
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W90220F
60
The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from
Version 0.84
Winbond.
0xf00002fa (COM2)
0
1
2
3
4
5
6
7
FMENo
RTHo[0:1]
DMOD
IID[0:2]
NOI
Bits 0
Status of "FIFO Mode Enable"
This bit echos if "FIFO mode" is enable or not. Since "FIFO mode" is always enable,
this bit always shows logical 1 when CPU reading this register.
Bit 1-2 Status of RX FIFO threshold level
These bits show current setting of receiver FIFO threshold level (RTH). The meaning of
RTH is defined in the following FCR description.
Bit 3
DMA mode select
The DMA function is
not implemented
in this version. Reading IIR, the bit-3 is always 0.
Bit 4-6 Interrupt Identification bits
The IID[0:2] along with NOI indicate current interrupt request from COM port
Bit 7
No Interrupt (NOI) pended
Table 5.2.5-3 : Interrupt Control Functions
IIR[4:7]
Priority
Interrupt Type
Interrupt Source
Interrupt Reset
control
- - - 1
0 1 1 0
--
None
None
--
Highest
Receiver Line
Status
(Irpt_RLS)
Overrun Error or
Parity Error or
Framing Error or
Break Interrupt
Receiver FIFO thres-
hold level is reached
Reading the LSR
0 1 0 0
Second
Received Data
Available
(Irpt_RDA)
Receiver FIFO
Time-out
(Irpt_TOUT)
Receiver FIFO drops
below the threshold
level
Reading the RBR
1 1 0 0
Second
Receiver FIFO is non-
empty and no
activities are occured
in receiver FIFO
during the TOR
defined time duration
Transmitter Holding
Register Empty
0 0 1 0
Third
Transmitter
Hoding Register
Empty
(Irpt_THRE)
Reading the IIR (if
source of interrupt is
Irpt_THRE) or
writing into the THR
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