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參數資料
| 型號： | W90220F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PA-RISC Embedded Micro-Controller(惠普PA-RISC結構的32位嵌入式微控制器) |
| 中文描述： | 32-BIT, 150 MHz, RISC PROCESSOR, PQFP208 |
| 封裝： | PLASTIC, QFP-208 |
| 文件頁數： | 20/79頁 |
| 文件大小： | 501K |
| 代理商： | W90220F |
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W90220F
20
The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from
Version 0.84
Winbond.
Features :
transmitter and receiver are each buffered with 16 bytes FIFO's to reduce the number of interrupts presented to
the CPU
MODEM control functions (CTS, RTS, DSR, DTR, RI and DCD)
Fully programmable serial-interface characteristics :
-- 5-, 6-, 7-, or 8-bit characters
-- even, odd, or no-parity bit generation and detection
-- 1-, 1&1/2, or 2-stop bit generation
-- baud rate generation
line break generation and detection
false start bit detection
full prioritize interrupt system controls
loop back mode for internal diagnostic testing
Related Pins :
(COM1)
- SIN1
- SOUT1 (output) : Serial data output to peripheral device or MODEM
- CTS1# (input) : Clear to send signal
- DSR1# (output) : Data set ready
- DTR1# (input) : Data terminal ready
- RTS1# (output) : Request to send
- DCD1# (input) : Data carrier detect
- RI1#
(output) : Ring indciator
(input) : Serial data input from peripheral device or MODEM
(COM2)
- SIN2
- SOUT2 (output) : Serial data output to peripheral device or MODEM
(input) : Serial data input from peripheral device or MODEM
Operation Modes :
- Interrupt Mode operation :
A. Receiver control :
- Set FCR[0:1] to select a proper receiver threshold level and then turn on "receiver data available
interrupt"
(Irpt_RDA) by set IER[7] to logic 1.
- The Irpt_RDA will be triggered when the receiver FIFO (RX-FIFO) has reached its programmed trigger
level, and it will be cleared as the available data in RX-FIFO drops below the trigger level.
- As Irpt_RDA occured, the corresponding IIR bits will be set to inform the software application that data
in RX-FIFO has reached programmed threshold level.
- If the received data has any errors, the "line status interrupt" (Irpt_RLS) will occur and has higher priority
than Irpt_RDA.
- If "time out interrupt" (Irpt_TOR) is enable by set IER[7] and TOR[0] to logic 1s. The Irpt_TOR will
occur, if the following conditions exist :
- at least one character is in RX-FIFO.
- RX-FIFO is not received any data or accessed by CPU from the most recent serial character received,
and the time period, counting by baud rate bit clock, has exceeded the value being programmed in
TOR[1:7].
- The Irpt_TOR and the time-out counter will be cleared as the CPU reads one character from RX-FIFO.
- The time-out counter is reset after a new character is received or after the CPU reads the RX-FIFO.
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