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參數(shù)資料
| 型號： | W90220F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PA-RISC Embedded Micro-Controller(惠普PA-RISC結(jié)構(gòu)的32位嵌入式微控制器) |
| 中文描述： | 32-BIT, 150 MHz, RISC PROCESSOR, PQFP208 |
| 封裝： | PLASTIC, QFP-208 |
| 文件頁數(shù)： | 65/79頁 |
| 文件大小： | 501K |
| 代理商： | W90220F |
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W90220F
65
The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from
Version 0.84
Winbond.
This bit is set to a logic 1 whenever the received character did not have a valid "parity bit".
Bit 6
Overrun Error indicator
An overrun error will occur only after the RX FIFO is full and the next character has been
completely received in the shift register. The ccharacter in the shift register is overwritten,
but it is not transferred to the RX FIFO. OE is indicated to the CPU as soon as it happens
and is reset whenever the CPU reads the contents of the LSR.
Bit 7
RX FIFO Data Ready
0 = RX FIFO is empty
1 = RX FIFO contains at least 1 received data word.
LSR[3:5] (BI, FE, PE) is revealed to the CPU when its associated character is at the top of the RX
FIFO. These three error indicators are reset whenever the CPU reads the contents of the LSR.
LSR[3:6] (BI, FE, PE, OE) are the error conditions that produce a "receiver line status interrupt"
(Irpt_RLS) when IER[5]=1. Read LSR clear Irpt_RLS.
Writing LSR is a null operation (not suggested).
Modem Status Register (MSR)
Port address : 0xf00003fe (COM1)
Read only
Power-on Default : ---
0xf00002fe (COM2)
0
1
2
3
4
5
6
7
DCD#
RI#
DSR#
CTS#
DDCD
TERI
DDSR
DCTS
Bits 0
Complement version of
Data Carrier Detect
(DCD#) input
Bits 1
Complement version of
Ring Indicator
(RI#) input
Bits 2
Complement version of
Data Set Ready
(DSR#) input
Bits 3
Complement version of
Clear to Send
(CTS#) input
Bits 4
DCD# state change
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