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參數資料
| 型號： | W90220F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PA-RISC Embedded Micro-Controller(惠普PA-RISC結構的32位嵌入式微控制器) |
| 中文描述： | 32-BIT, 150 MHz, RISC PROCESSOR, PQFP208 |
| 封裝： | PLASTIC, QFP-208 |
| 文件頁數： | 64/79頁 |
| 文件大小： | 501K |
| 代理商： | W90220F |
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W90220F
64
The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from
Version 0.84
Winbond.
Line Status Register (LSR)
Port address : 0xf00003fd (COM1)
Read only
Power-on Default : ---
0xf00002fd (COM2)
0
1
2
3
4
5
6
7
Err_RCVR
TEMT
THRE
BI
FE
PE
OE
DR
Bits 0
RX FIFO Error
0 = RX FIFO works normally
1 = There is at least one parity error (PE), framing error (FE) or break indication (BI)
in the FIFO. LSR[0] is cleared when CPU reads the LSR and if there are no sub-
sequent errors in the RX FIFO.
Bit 1
Transmitter Empty
0 = Either Transmitter Holding Register (
THR
- TX FIFO) or Transmitter Shift Register
(
TSR
) are not empty.
1 = Both THR and TSR are empty.
Bit 2
Transmitter Holding Register Empty
0 = THR is not empty.
1 = THR is empty.
The THRE bit is set when the last data word of TX FIFO is transferred to TSR. This bit is reset
concurrently with the loading of the THR (or TX FIFO) by the CPU. This bit also causes the
UART to issue an interrupt (Irpt_THRE) to the CPU when IER[6]=1.
Bit 3
Break Interrupt indicator
This bit is set to a logic 1 whenever the received data input is held in the "spacing state"
(logic 0) for longer than a full word transmission time (that is, the total time of "start bit"
+ data bits + parity + stop bits).
Bit 4
Framing Error indicator
This bit is set to a logic 1 whenever the received character did not have a valid "stop bit"
(that is, the stop bit following the last data bit or parity bit is detected as a logic 0).
Bit 5
Parity Error indicator
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