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參數資料
| 型號： | W90220F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PA-RISC Embedded Micro-Controller(惠普PA-RISC結構的32位嵌入式微控制器) |
| 中文描述： | 32-BIT, 150 MHz, RISC PROCESSOR, PQFP208 |
| 封裝： | PLASTIC, QFP-208 |
| 文件頁數： | 62/79頁 |
| 文件大小： | 501K |
| 代理商： | W90220F |
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W90220F
62
The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from
Version 0.84
Winbond.
Line Control Register (LCR)
Port address : 0xf00003fb (COM1)
Read/Write
Power-on Default : 0x0
0xf00002fb (COM2)
0
1
2
3
4
5
6
7
DLAB
BREAK
SPAR
EPAR
PAR
STOP
WLEN
Bits 0
Divisor Latch Access Bit
0 = "2F8/3F8" and "2F9/3F9" are used to access RBR, THR or IER.
1 = "2F8/3F8" and "2F9/3F9" are used to access Divisor Latch Registers (DLL, DLM).
Bit 1
Break Control Bit
When this bit is set to a logic 1, the serial data output (SOUT) is forced to the
Spacing State
(logic 0). This bit affects SOUT only and has no effect on the transmitter logic.
Bit 2
Stick Parity Enable
0 = Disable Stick Parity
1 = The parity bit is transmitted and checked as a logic 1 if bit-3=0 (odd parity), or
as a logic 0 if bit-3=1 (even parity).
This bit has effects only when bit-4 (Parity Bit Enable) is set.
Bit 3
Even Parity Enable
0 = Odd number of logic 1s is transmitted or checked in the data word bits and parity bit.
1 = Even number of logic 1s is transmitted or checked in the data word bits and parity bit.
This bit has effects only when bit-4 (Parity Bit Enable) is set.
Bit 4
Parity Bit Enable
0 = Praity bit is not generated (transmit data) or checked (receive data) during transfer.
1 = Parity bit is generated of checked between the "last data word bit" and "stop bit" of
the serial data.
Bit 5
Number of "Stop bit"
0 = One "stop bit" is generated in the transmitted data.
1 =
One and a half
"stop bit" is generated in the transmitted data when
5-bit
word length
is selected.
Two
"stop bit" is generated when
6-, 7-
and
8-bit
word length is selected.
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