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參數(shù)資料
| 型號： | W90220F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PA-RISC Embedded Micro-Controller(惠普PA-RISC結(jié)構(gòu)的32位嵌入式微控制器) |
| 中文描述： | 32-BIT, 150 MHz, RISC PROCESSOR, PQFP208 |
| 封裝： | PLASTIC, QFP-208 |
| 文件頁數(shù)： | 8/79頁 |
| 文件大小： | 501K |
| 代理商： | W90220F |
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W90220F
8
The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from
Version 0.84
Winbond.
PDA[31:0]
I/O
44-46, 48, 50,
53-55, 57, 58,
60, 62, 64-67,
81-85, 87, 88,
90, 92-94, 96,
98-101,
PCI tri-state Address/Data bus, Address and Data are
multiplexed on the same PCI pins. A bus transaction consists
of an address phase followed by one or more data phases.
PCI supports both read and write bursts. The address phase
is the clock cycle in which FRAME# is asserted. During the
address phase PDA[31:0] contain a physical address. During
data phases PDA[7:0] contain the least significant byte (lsb)
and PDA[31:24] contain the most significant byte (msb).
Write data is stable and valid when IRDY# is asserted and
read data is stable and valid when TRDY# is asserted. Data
is transferred during those clocks where both IRDY# and
TRDY# are asserted.
PCI Stop indicates the current target is requesting the master
to stop the current transaction.
PCI Target Ready indicates the selected device
complete the current data phase of the transaction. A data
phase is completed on any clock both TRDY# and IRDY# are
sampled asserted. During a read, TRDY# indicates that valid
data is present on PDA[31:0]. During a write, it indicates the
target is prepared to accept data. Wait cycles are inserted
until both IRDY# and TRDY# are asserted together.
PCI Device Select, when actively driven, indicates the
driving device has decoded its address as the target of the
current access. As an input, DEVSEL# indicates whether any
device on the bus has been selected.
PCI Bus Command and Byte Enables are multiplexed on the
same PCI pins. During the address phase of a transaction,
C/BE[3:0]# define the bus command. During the data phase
C/BE[3:0]# are used as Byte Enables. The Byte Enables are
valid for the entire data phase and determine which byte
lanes carry meaningful data. C/BE[0]# applies to byte 0 (lsb)
and C/BE[3]# applies to byte 3 (msb).
PCI Cycle Frame is driven by the current master to indicate
the beginning and duration of an access. FRAME# is
asserted to indicate a bus transaction is beginning. While
FRAME# is asserted, data transfers continue. When FRAM#
is deasserted, the transaction is in the final data phase or has
completed.
PCI Initiator Ready indicates the bus master
complete the current data phase of the transaction. A data
phase is completed on any clock both IRDY# and TRDY# are
sampled asserted. During a write, IRDY# indicates that valid
data is present on PDA[31:0]. During a read, it indicates the
master is prepared to accept data. Wait cycles are inserted
until both IRDY# and TRDY# are asserted together.
STOP#
I/O
76
TRDY#
I/O
72
ability to
DEVSEL#
I/O
74
C/BE[3:0]#
I/O
56,68,80,91
FRAME#
I/O
69
IRDY#
I/O
70
ability to
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