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參數資料
| 型號： | W90220F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PA-RISC Embedded Micro-Controller(惠普PA-RISC結構的32位嵌入式微控制器) |
| 中文描述： | 32-BIT, 150 MHz, RISC PROCESSOR, PQFP208 |
| 封裝： | PLASTIC, QFP-208 |
| 文件頁數： | 16/79頁 |
| 文件大小： | 501K |
| 代理商： | W90220F |
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W90220F
16
The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from
Version 0.84
Winbond.
dma transfer between pci memory to/from system memory are also support
4 words (16 bytes) memory burst-access; linear burst order
build-in 4-words data FIFO to accelerate memory access
the starting address of source and target shall be halfword boundary for 16-bit memory transfer and word
boundary for 32-bit memory transfer
Related Pins :
There are 19 pins allocated for two external dma slots to do 8-bit io-to-memory dma transfer. These pins include 8-
bit bi-directional data bus as well as 11control/status pins.
- DREQ0, DREQ1 (input) :
Set high by external dma devices of slot 0 and slot 1 respectively to request dma 8-bit io-to-memory transfer.
The DREQ(s) shall keep asserted (logic 1) during "demand mode" transfering, while during "block mode"
transfering the DREQ(s) shall be deasserted (logic 0) after their corresponding DACK(s) is granted and before
the end of dma block transfering.
- DACK0, DACK1 (output) :
Set high by the dma controller to acknowledge the dma DREQ(s) from dma slot 0 and slot1 respectively.
Whenever DACK(s) is set high, the dma transfer is on-going.
- TC0, TC1 (output) :
At the end of the last byte of dma transfer, the TC(s) will be pulse high for 1 system clock immediately
indicating that dma transfer is finished.
- DMARDY (input) :
This signal is used by external dma devices to insert wait states when the devices being progrmming by cpu.
DMARDY is an open collector signal which shall be pull-up externally (default "don't insert any wait states").
If any devices need to lengthen the IOR or IOW cycle, it must drive DMARDY to logic high within one system
clock after IOR or IOW signal being set high.
- IOR (output) :
This signal is pulsed high indicating an IO read command cycle is on-going whether in cpu mode (DACK(s)
= 0s) or in dma mode (DACK(s) = 1).
- IOW (output) :
This signal is pulsed high indicating an IO write command cycle is on-going whether in cpu mode (DACK(s)
= 0s) or in dma mode (DACK(s) = 1).
- CS0, CS1 (output) :
These two signals are Chip Selects of dma slot 0 and slot 1. As dma controller wants to programming dma
devices, it must drive the corresponding CS(s) to logic high.
- DD[0:7] (in/out) :
Birdirectional 8-bit data bus with bit 0 is the most significant bit.
Operation Modes :
(Left for Blank)
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