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參數(shù)資料
| 型號(hào)： | W90220F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PA-RISC Embedded Micro-Controller(惠普PA-RISC結(jié)構(gòu)的32位嵌入式微控制器) |
| 中文描述： | 32-BIT, 150 MHz, RISC PROCESSOR, PQFP208 |
| 封裝： | PLASTIC, QFP-208 |
| 文件頁(yè)數(shù)： | 53/79頁(yè) |
| 文件大小： | 501K |
| 代理商： | W90220F |
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W90220F
53
The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from
Version 0.84
Winbond.
Bit 6
"nFault" Interrupt (Irpt_nFault) enable
0 = Mask Irpt_nFault
1 = Enable Irpt_nFault
Bit 7
Loop back enable
0 = Loop-back disable
1 = Loop-back enable
During Loop-Back mode, {nStrobe, nAutoFd, nInit, nSelectIn} will be fed to
{nAck, Busy, PError, nFault} internally. This mode is used only for test issue.
Interrupt Identification Register (IIR)
Port address : 0xf000037e
Read only
Power-on Default : ---
0
1
2
3
4
5
6
7
Reserved
Irpt_Tout
Irpt_TC
Irpt_Temp Irpt_RDA Irpt_nFaul
t
Irpt_nAck
Bits 2
Time-Out Interrupt flag
"Set" situation
: If IER[2] is set, and "Time out" is occured during parallel port
transfering.
"Reset" situation : Reset device, or CPU reads Time-Out Register (TOR) or Dfifo
being accessed either by CPU or parallel port interface transfering.
Bits 3
DMA Terminal Count Interrupt flag
"Set" situation
: If IER[3] is set, and TC is asserted by DMA controller once DMA
transfer is done.
"Reset" situation : TC is deasserted by DMA controller.
Bits 4
Dfifo Empty Interrupt flag
"Set" situation
: If IER[4] is set, and Dfifo is empty during "
forward transfering
".
"Reset" situation : CPU write new data into Dfifo.
Bits 5
Dfifo Read Threshold Interrupt flag
"Set" situation
: If IER[5] is set, and data bytes received by Dfifo are exceeded the
threshold level (defined in FCR[4:5] ) during "
reverse transfering
".
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