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參數(shù)資料
| 型號(hào)： | W90220F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PA-RISC Embedded Micro-Controller(惠普PA-RISC結(jié)構(gòu)的32位嵌入式微控制器) |
| 中文描述： | 32-BIT, 150 MHz, RISC PROCESSOR, PQFP208 |
| 封裝： | PLASTIC, QFP-208 |
| 文件頁數(shù)： | 11/79頁 |
| 文件大小： | 501K |
| 代理商： | W90220F |
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W90220F
11
The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from
Version 0.84
Winbond.
SOUT1
O
2
COM1 serial data output to the communication link (modem
or peripheral device).
COM1 clear to send signal
COM1 data set ready
COM1 data terminal ready
COM1 request to send
COM1 data carrier detect
COM1 ring indicator
CTS1n
DSR1n
DTR1n
RTS1n
DCD1n
RIN1n
COM2 Serial Port Signal
SIN2
I
I
O
O
I
I
208
207
3
4
205
206
I
6
COM2 serial data input from the communication link (modem
or peripheral device).
COM2 serial data output to the communication link (modem
or peripheral device).
SOUT2
O
5
Synchronous Serial Port Signal
SDI
SDO
SYNC
I
O
I/O
113
118
116
Serial data-in from a external codec device
Serial data-out to a exteral codec device
Frame sync of SDI/SDO. This signal is an input signal during
"slave mode" or output signal during "master mode"
Serial Clock for SDI/SDO transfering. This signal is an input
signal during "slave mode" or output signal during "master
mode"
SCLK
I/O
114
Miscellaneous
WAKEUP
/INTR0
I
51
If MD[24] is pull down, this pin serves as an external interrupt
request. A active high-state in this pin will make EIER[12] be
set. In this mode, this pin can also serve as an interrupt
request pin for an IDE slot.
If MD[24] is pull high, this pin serves a "resume" request to
wake up the chip from "DOZE" mode.
If MD[24] is pull down, this pin serves as an external interrupt
request. A active high-state in this pin will make EIER[13] be
set. In this mode, this pin can also serve as an interrupt
request pin for an IDE slot.
If MD[24] is pull high, this pin serves a "resume" request to
wake up the chip from "SLEEP" mode.
RESUME
/INTR1
I
52
Power/Ground pin
VDD5V
VDDp
I
I
12,110
8,31,49,61,73
,89,112,133,
152,169,192
26,75,136,18
3
198
200
33,63,95,117,
146,165,196,
10,29,47,59,
71,86,97,115,
131,149,167,
180,194
5.0V Vdd (for a mixed 5.0V/3.3V enviornment)
Global 3.3V Vdd
VDDi
I
3.3V Vdd (for internal logic only)
VDDl
VSSl
VSSi
I
I
I
3.3V Vdd (for internal PLL logic)
VSS (for internal PLL logic)
VSS (for internal logic)
VSSp
I
Global VSS
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