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參數資料
| 型號： | W90220F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PA-RISC Embedded Micro-Controller(惠普PA-RISC結構的32位嵌入式微控制器) |
| 中文描述： | 32-BIT, 150 MHz, RISC PROCESSOR, PQFP208 |
| 封裝： | PLASTIC, QFP-208 |
| 文件頁數： | 7/79頁 |
| 文件大小： | 501K |
| 代理商： | W90220F |
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W90220F
7
The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from
Version 0.84
Winbond.
3.2 DETAILED PIN DESCRIPTIONS
The following abbreviations are used for pin types in the following sections : (I) indicates inputs; (O) indicates
outputs; (I/O) indicates a bidirectional signal; (TS) indicates three-state; (OC) indicates open collector.
PIN Name
CPU Signal
PWRON
PLLOSC
OSC
PCI LOCAL BUS
DIR
PIN #
DESCRIPTION
I
I
I
30
199
132
CPU Power-On reset input, high active
14.318Mhz Oscillator input for internal PLL
14.318Mhz Oscillator input for Timer, UART
for more detail description of the PCI signals please refer to the
PCI LOCAL
BUS SPECIFICATION
PCI Interrupt input, level senstive, low active signal. Once
the INTx# signal is asserted, it remains asserted until the
device driver clear the pending request. When the request is
cleared, the device deasserts its INTx# signal.
PCI Request input, indicates to the PCI arbiter that this agent
desires use of the bus.
PCI Grant output, indicates to the agent that access to the
bus has been granted.
PCI Reset output, is used to bring PCI-specific registers,
sequencers, and signals to a consistent state. Low active.
PCI Clock output, provides timing for all transactions on PCI
and is an input to every PCI device.
PCI System Error is for reporting address parity errors, data
parity errors on the Special Cycle command, or any other
system error where the result will be catastrophic. The
assertion of SERR# is synchronous to the clock and meets
the setup and hold times of all bused signals.
PCI Parity Error is only for the reporting of data parity errors
during all PCI transactions except a Special Cycle. The
PERR# pin is sustained tri-state and must be driven active
by the agent receiving data two clocks following the data
when a data parity error is detected. The minimum duration
of PERR# is one clock for each data phase that a data parity
error is detected. An agent cannot report a PERR# until it
has claimed the access by asserting DEVSEL# (for a target)
and completed a data phase or is the master of the current
transaction.
INTA#
INTB#
INTC#
INTD#
PREQ0#
PREQ1#
GNT0#
GNT1#
PCIRST#
I
102
103
104
105
42
43
40
41
7
I
O
O
PCICLK
O
9
SERR#
I
78
PERR#
I/O
77
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