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參數(shù)資料
型號: W90220F
廠商: WINBOND ELECTRONICS CORP
元件分類: 微控制器/微處理器
英文描述: PA-RISC Embedded Micro-Controller(惠普PA-RISC結(jié)構(gòu)的32位嵌入式微控制器)
中文描述: 32-BIT, 150 MHz, RISC PROCESSOR, PQFP208
封裝: PLASTIC, QFP-208
文件頁數(shù): 35/79頁
文件大小: 501K
代理商: W90220F
W90220F
35
The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from
Version 0.84
Winbond.
0
1
2
3
4
5
6
7
REFRAT[0:1]
CD2RD
RA2CD[0:1]
CA2RA
CASRD[0:1]
Bits 0-1 Refresh Rate (REFRAT[0:1])
REFRAT[0:1] determine the frequence of DRAM refresh cycles.
(Table 5.2.1-9 The frequence of DRAM refresh cycles)
REFRAT[0:1]
Frequence of refresh cycle
(us)
0 0
0 1
1 0
1 1
15
60
240
960
Bit 2
CAS# deassertion to RAS# deassertion (CD2RD)
0 = The delay time for CAS# deassertion to RAS# deassertion is
1
SYSCLK
for CAS-before-RAS refresh cycle.
1 = The delay time for CAS# deassertion to RAS# deassertion is
2
SYSCLK
for CAS-before-RAS refresh cycle.
Bits 3-4 RAS# assertion to CAS# deassertion (RA2CD[0:1])
These two bits determine the duration between RAS# assertion to CAS# deassertion for CAS-
before-RAS refresh cycle.
(Table 5.2.1-10 Delay time from RAS# assertion to CAS# deassertion)
RA2CD[0:1]
Delay (SYSCLK)
0 0
0 1
1 0
1 1
1
2
3
4
Bit 5
CAS# assertion to RAS# assertion (CA2RA)
0 = The delay time for CAS# assertion to RAS# assertion is
1
SYSCLK
for CAS-before-RAS refresh cycle.
1 = The delay time for CAS# assertion to RAS# assertion is
2
SYSCLK
for CAS-before-RAS refresh cycle.
Bits 6-7 CAS# active time during DRAM-read (CASRD[0:1])
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