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參數資料
| 型號： | W90220F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PA-RISC Embedded Micro-Controller(惠普PA-RISC結構的32位嵌入式微控制器) |
| 中文描述： | 32-BIT, 150 MHz, RISC PROCESSOR, PQFP208 |
| 封裝： | PLASTIC, QFP-208 |
| 文件頁數： | 19/79頁 |
| 文件大小： | 501K |
| 代理商： | W90220F |
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W90220F
19
The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from
Version 0.84
Winbond.
- Select (input) :
Compatible Mode : Set high to indicate that the peripheral device is on-line.
ECP Mode
: Used by peripheral to reply to the requested extensibility byte sent by the host during the
negotiation phase.
- nFault (input) :
Compatible Mode : Set low by peripheral device to indicate that an error has occured.
ECP Mode
: Set high to acknowledge 1284 compatibility during negotiation phase. During ECP mode
the peripheral may drive this pin low to request communications with the host. This signal
would be typically used to generate an interrupt to the host. This signal is valid in both
forward and reverse trnasfers.
- ED[0:7] (in/out) : 8-bit bus used to hold data, address or command information in all modes. The bit 0 is the
most significant bit.
Operation Modes :
(Left for Blank)
5.1.5 UART
Overview :
The W90220 contains two Universal Asynchronous Receiver/Transmitter (UART) ports, one of them provides
complete MODEM-control and serial transfermation capabilities, whereas the other one provides only serial
transfermation capability. The UART performs serial-to-parallel conversion on data characters received from a
peripheral device such as MODEM, and parallel-to-serial conversion on data characters received from the CPU.
One 16 bytes transmitter FIFO (TX-FIFO) and one 16 bytes (plus 3 bits of error data per byte) receiver FIFO (RX-
FIFO) have been built in to reduce the number of interrupts presented to the CPU. The CPU can read the complete
status of the UART at any time during the functional operation. Status reported includes error conditions (parity,
overrun, framing, or break interrupt) and states of TX-FIFO and RX-FIFO.
Block Diagram :
TX-FIFO (16x8)
& Control
Baud Rate
Generator
32-bit CPU bus
TX shift register
RX-FIFO (16x8)
& Control
RX shift register
SDI
SDO
8
8
Fig 5.1.5-1 UART Block Diagram
OSC (14.318Mhz)
RTS#
DTR#
OUT1#
OUT2#
CTS#
DSR#
DCD#
RI#
Modem
Control
Reg
Modem
Status
Reg
8
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