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參數(shù)資料
| 型號： | W90220F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PA-RISC Embedded Micro-Controller(惠普PA-RISC結(jié)構(gòu)的32位嵌入式微控制器) |
| 中文描述： | 32-BIT, 150 MHz, RISC PROCESSOR, PQFP208 |
| 封裝： | PLASTIC, QFP-208 |
| 文件頁數(shù)： | 23/79頁 |
| 文件大小： | 501K |
| 代理商： | W90220F |
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W90220F
23
The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from
Version 0.84
Winbond.
- The shifting data bits on SDI and SDO are always MSB first.
- If serial word length is not 16 or 32, it is software responsibility to left(MSB) justify the transmit
data words before writing it to transmit FIFO, the received data before being written into receive
FIFO is righ(LSB) justified automatically by SSI module where the unfilled MSBs are catneted
with logic 0s.
- SSI module always shifts out logic 0s on each frame sync if transmit FIFO is empty at that time.
- A receiver FIFO interrupt will be asserted (when RX-FIFO interrupt is enable) if the received
data words exceeds the receive FIFO's threshold level. Likewise, a transmitter FIFO interrupt
will be asserted (when TX-FIFO interrupt is enable) if the available data words in transmit FIFO
is lower than its threshold level.
- Fig 6.1.5-2 shows a standard long framing transfer where serial word length is 3 (CFGH[8:11] =
2), words per frame is 3 (CFGH[12:15]=2) and bits per frame is 9 (CFGL[0:7] = 10).
SYNC
SDI
D1_1
D1_2
D1_3
D2_1
D2_2
D2_3
D3_1
D3_2
D3_3
D1_1
D1_2
SDO
D1_1
D1_2
D1_3
D2_1
D2_2
D2_3
D3_1
D3_2
D3_3
D1_1
D1_2
SCLK
Fig 5.1.6-2 SSI long framing transfer
- Short Framing : When CFGH[3] is set to logic 0, SSI is operated in long framing mode. The following features
are included in short framing mode
consists of the following features.
- The frame sync (SYNC) is asserted for one SCLK immediately before the first bit of transmit
and receive data.
- The frame sync (SYNC) is asserted for one SCLK period.
- All other features are the same as long framing mode.
- Fig 6.1.5-3 shows a standard short framing transfer where serial word length is 3 (CFGH[8:11] =
2), words per frame is 3 (CFGH[12:15]=2) and bits per frame is 9 (CFGL[0:7] = 10).
SYNC
SDI
D1_1
D1_2
D1_3
D2_1
D2_2
D2_3
D3_1
D3_2
D3_3
D1_1
D1_2
SDO
D1_1
D1_2
D1_3
D2_1
D2_2
D2_3
D3_1
D3_2
D3_3
D1_1
D1_2
SCLK
Fig 5.1.6-3 SSI short framing transfer
5.1.7 TIMER CHANNELS
Overview :
(Left for Blank)
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