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參數(shù)資料
| 型號： | W9310 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | Direct Sequence Spread Spectrum Transceiver(直接序列擴展頻譜收發(fā)器) |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP80 |
| 封裝： | PLASTIC, QFP-80 |
| 文件頁數(shù)： | 10/36頁 |
| 文件大小： | 220K |
| 代理商： | W9310 |
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W9310
- 10 -
FUNCTIONAL DESCRIPTION
The W9310 is made up of six functional modules. These include the serial bus interface (SBI), the
receiver, the transmitter, the time-division duplex (TDD) controller, the transmit and receive FIFOs,
and the master clock generator. The SBI module supports bidirectional communication with a
microprocessor such as the Winbond W921F880 or equivalent. The receiver module performs all the
digital signal processing required by the spread spectrum receiver, including de-correlation and
demodulation. The transmit module generates the spread spectrum binary sequence for output to an
RF modulator. The TDD controller includes logic implementing the ping-pong protocol and various
handshaking and interface signals. The transmit and receive FIFOs are used to buffer the transmit
and receive data in full-duplex voice and data mode. The master clock generator generates clock
signals required to drive the various modules of the W9310.
Each of these modules is described in more detail below.
SBI
The serial bus interface (SBI) allows the W9310 to communicate bidirectionally with a
microprocessor. At power on, the W9310 receives programming information from the microprocessor.
In TDD operation, the SBI can generate two interrupts, one for remote signaling by the
microprocessor, the other for delivering the internally accumulated signal-to-noise (SN) measure to
the microprocessor.
Receiver
The receiver samples the incoming baseband signals at two samples per PN chip. The samples are
correlated with four possible PN sequences in 64-bit parallel correlators. The de-correlated signal is
demodulated via a digital phase locked loop. The receiver is powered down while the W9310 is
transmitting.
In addition, the receiver consumes peak power only during the brief period of the initial acquisition.
After acquisition, the receiver goes into tracking/detection mode, and the power consumption of the
receiver module is reduced by two orders of magnitude.
Transmitter
The transmitter logic encodes two consecutive bits of data into one of four possible 32-bit PN
sequences. The PN sequences are programmed by the microprocessor through the SBI. The
transmitted PN sequence is further randomized by modulus-2 addition with a 2047-bit PN sequence.
This operation smoothes the output spectrum of the transmitted signal and eliminates discrete
spectral components.
During ping-pong operation, to reduce power consumption, the transmitter remains idle when the
W9310 is in receive mode. The transmitter outputs a tri-state buffer and is in high-impedance state
during this idle time.
TDD Controller
The time-division duplex (TDD) controller implements the ping-pong protocol that allows a full-duplex
link to be emulated by a half duplex radio. The TDD controller also generates appropriate clock and
control signals to other modules of the W9310. In full-duplex mode, the TDD controller multiplexes
and de-multiplexes the overhead bits with the real data. It also uses a digital locked loop to maintain
an equal read and write rate to the FIFOs to prevent FIFO overflow or underflow. In addition, the TDD
controller contains logic to generate the proper handshaking signals for both voice and data
communication.
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