
W9310
- 14 -
Preamble
Unique Word (UW)
Status Nibble (ST)
Data
32
22
4
288
Figure 1. Burst Frame Structures
Each actual burst cycle also includes two guard times to allow for both propagation and RF
transceiver switching time. G
1
is 32-bit delay between the time when the master stops transmission
and when the slave commences transmission; G
2
is a 32-bit delay between the time when the slave
stops transmission and when the master commences transmission. These guard times allow for a 375
μ
S delay (for a master oscillator frequency of 16.384 MHz). The total burst cycle is 768 bits long,
including a 12-bit internal delay (the transmitter turns off 6 bits after the last data bit is latched to the
transmitter; the master and the slave therefore contribute a total of a 12-bit internal delay).
During the ping-pong operation, the receiver goes through several stages. Initially, when the 4 UWs
of the acquisition burst have been received and decoded correctly, the receiver (either master or
slave) declares "locked" (the LOCK signal output is asserted). After an empty burst has been
decoded, the receiver declares "locked" (the RLCOK signal output is asserted), signifying that the
remote device has locked. The behavior of the receiver after establishing the RLOCK condition
depends on whether the internal state machine is turned on (determined by the setting of the
configuration word, bit CI12). When the state machine is turned off, transmission will be turned off
whenever the UW is not detected. The slave then waits for a new acquisition burst while the master
will start the acquisition cycle again by transmitting an acquisition burst. Note that the master will
continue to broadcast acquisition bursts until it has received a proper acquisition burst from the slave
in response. The master will always revert back to the initial acquisition mode (broadcasting
acquisition bursts), whenever it fails to detect the proper UWs from the slave.
If the state machine is turned on, then the receiver will not declare LOCK loss right after UW failed to
be detected. Instead, it will allow for UW errors in up to two further bursts before declaring LOCK loss.
The state diagram for this lock state machine is shown in Figure 2. In the figure, UW4DET indicates
the condition when the four UWs have been detected during the acquisition burst, and UWDET
indicates the condition where the single UW is empty and data bursts have been detected. M_SB is
the programmed bit (CI8), which is a binary "1" when the W9310 is programmed to be the master and
a binary "0" when it is programmed as a slave. NMODE is a signal generated by the receive logic and
is asserted when the digital phase locked loop in the receiver has achieved lock. NMODE is similar to
an RSSI signal. Note that the NMODE signal is independent of the UW detection. Physically, when
NMODE is asserted, it indicates that PN acquisition has been achieved. The LOCKED and RLOCK
states are as described above.