- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄363908 > W9310 (WINBOND ELECTRONICS CORP) Direct Sequence Spread Spectrum Transceiver(直接序列擴(kuò)展頻譜收發(fā)器) PDF資料下載
參數(shù)資料
| 型號(hào)： | W9310 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Direct Sequence Spread Spectrum Transceiver(直接序列擴(kuò)展頻譜收發(fā)器) |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP80 |
| 封裝： | PLASTIC, QFP-80 |
| 文件頁(yè)數(shù)： | 21/36頁(yè) |
| 文件大小： | 220K |
| 代理商： | W9310 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)當(dāng)前第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)
W9310
Publication Release Date: July 1996
- 21 -
Revision A3
Reading the Status Nibble and S/N Data from SBI
The status nibble (TXSTAT) and S/N register data are updated periodically by the W9310. Once a
status nibble or an S/N value has been loaded onto the register by the W9310, interrupts IRQ1_N or
IRQ2_N are asserted. Once an interrupt has been asserted, no new data will be loaded onto the
register until the interrupt has been serviced and cleared by the microprocessor. The status nibble is
updated once every burst (if IRQ1_N is serviced every burst). The S/N data are calculated from the
AGC circuit inside the W9310 once every 128 data bits (including overhead bits).
To read the status nibble and the S/N value, the following actions need to performed:
1. The microprocessor sets the address of the register to be read (0 for status nibble, 1 for S/N data)
on the ADDR pins.
2. The microprocessor selects the W9310 by asserting the CHIPSEL_N pin.
3. The microprocessor clocks the SCLK pin the appropriate number of clock cycles (4 for status
nibble,
and 8 for S/N data). The status nibble or the S/N data byte is clocked out serially on
the SDO pin.
The data (from MSB to LSB) are clocked out of the W9310 on the falling edge of the SCLK clock.
4. The microprocessor clears the appropriate interrupt by toggling the LATCH signal once.
5. The microprocessor sets the address of the register to an unused address and releases
CHIPSEL_N signal.
An example of the interrupt service timing is shown in Figure 9.
SCLK
ADDR
15H
2H
15H
MSB
LSB
SDO
LATCH
CHIPSEL_N
IRQ1_N
Figure 9. Interrupt Service Timing
Note that the SDO pin is a tri-state output pin and will remain in high impedance state until either
address 0 or 1 is selected and CHIPSEL_N is asserted. Also note that the SBI are not affected by the
reset signals, the only exception being status nibble, which cannot be loaded when the reset signal,
RST2_N, is asserted.
SBI Registers
A total of fifteen registers are available for storing programming information through the SBI. These
registers are listed below:
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W9320 | ADPCM Codec(ADPCM編解碼器) |
| W9321 | ADPCM Codec(ADPCM編解碼器) |
| W9330F | Code Division Spread Spectrum Cordless Telephone Controller(具有編碼分劃和擴(kuò)展頻普技術(shù)的無繩電話控制器) |
| W934GD5V | THE GREEN SOURCE COLOR DEVICES ARE MADE WITH GALLIUM PHOSPHIDE GREEN LIGHT EMITTING DIODE |
| W93902 | POCSAG Decoder For Pagers(尋呼機(jī)的POCSAG 解碼器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W9310-16C64RC | 制造商:Winslow Adaptics Ltd 功能描述:40 way DIL to 44 way PLCC socket,16C64 |
| W9310-17C42RC | 制造商:Winslow Adaptics Ltd 功能描述:40 way DIL to 44 way PLCC socket,17C42 |
| W9310RC | 制造商:Winslow Adaptics Ltd 功能描述:40way DIL to 44way PLCC socket,2.1x1.2in |
| W9312 | 制造商:Apex Tool Group 功能描述:3/4 IN. X 12 FT MEZURALL POWER RETURN TAPE |
| W9312D | 制造商:Apex Tool Group 功能描述:3/4 IN. X 12 FT MEZURALL POWER RETURN TAPE, 10THS AND 100THS |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。