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參數資料
| 型號： | W9310 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 通信及網絡 |
| 英文描述： | Direct Sequence Spread Spectrum Transceiver(直接序列擴展頻譜收發器) |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP80 |
| 封裝： | PLASTIC, QFP-80 |
| 文件頁數： | 31/36頁 |
| 文件大小： | 220K |
| 代理商： | W9310 |
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W9310
Publication Release Date: July 1996
- 31 -
Revision A3
APPLICATION INFORMATION
In this section, several issues concerning the application of the W9310 are discussed.
Notes on Half-duplex Operation
In the half-duplex mode, because of the hysteresis of the digital PLL, the DCD_N signal is not de-
asserted right away. On average, it takes from 21 to 30 symbols (or 42 to 60 bits) before DCD_N is
de-asserted. During this time, the W9310 will deliver random data on the RX pin. The receiver will not
declare lock (asserting DCD_N) until the initial acquisition process has been completed. This process
typically takes from 60-110 bits depending on the condition of the radio link. It is imperative,
therefore, for the packet to carry framing information so that the beginning and end of the packet can
be detected (for example, a high-speed synchronous data link protocol such as HDLC provides its
own framing structure in the packets it transmitted). In addition, sufficient preamble bits must be
transmitted prior to actual data transmission so that the receiver will be locked and ready to deliver
data when actual data arrive.
Selecting the Master Oscillator Frequency
A complete clock generator has been included on the W9310 to reduce the system clocking
requirement. Nominally, only a single crystal or clock oscillator is required for powering the entire
W9310. The required crystal or clock oscillator frequency is dependent on the data rate and in
general can be calculated from the following equations:
f
2048
×
f
8
×
f
bclk
for full-duplex voice
f
512
f
osc
data
=
×
f
f
osc
data
=
×
192
osc
=
frame
=
for full-duplex data (5)
for half-duplex data
Where f
osc
is the master oscillator frequency, f
frame
is the framing clock of the ADPCM codec, f
bclk
is bit-
rate clock of the ADPCM codec, and f
data
is the data rate. For example, for a 32 Kbps ADPCM voice,
f
frame
= 8 KHz, f
bclk
= 2.048 MHz, and the required f
osc
is 16.384 MHz. For 64 Kbps full-duplex data, f
data
=
64 Kbps and the required master oscillator frequency is 32.768 MHz. For 160 Kbps half-duplex data, f
data
= 160 Kbps and the required master oscillator frequency is 30.72 MHz.
Programming the W9310
This section briefly discusses how to program the W9310 for various operating modes. First, loading
of PN sequences A, B, C, and D is required for operation in all modes. These are loaded from MSB to
LSB. For full-duplex operation, the 22-bit UW is loaded into the SBI from MSB to LSB. The CI bits
must be loaded for any operating mode. Note that the loading order of the CI bits is the
opposite
of
that for the PN and UW sequences, which are loaded from LSB to MSB. The CI bits configure the
various programmable parameters in the receiver. In general, for normal operation, CI0 and CI1 must
be set to low.
The programming of PLSL, CNTLR, ACC1RES, and WSL depends on several environmental and
system-related factors. For example, the size of the PLSL and CNTLR windows affects the dynamic
performance of the PLL. In general, if a smaller window size is used, the PLL will behave as if it has a
smaller loop bandwidth with higher noise filtering but at the expense of slower dynamic response. If a
larger window size is used, the PLL will respond quicker dynamically but its performance will be
degraded because more noise is allowed to enter the system.
Note that the width of the central zone
must be smaller than or equal to the size of the ESD window
(this means that the ESD window size
must not be set to 8, a value included for testing purposes only). Similarly, the width of the detection
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