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參數資料
| 型號： | W9310 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 通信及網絡 |
| 英文描述： | Direct Sequence Spread Spectrum Transceiver(直接序列擴展頻譜收發器) |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP80 |
| 封裝： | PLASTIC, QFP-80 |
| 文件頁數： | 7/36頁 |
| 文件大小： | 220K |
| 代理商： | W9310 |
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W9310
Publication Release Date: July 1996
- 7 -
Revision A3
Pin Description, continued
SYMBOL
FCLK_RT
PIN
22
I/O
O
FUNCTION
Receive clock/Framing clock. In synchronous mode, FCLK_RT is
used to synchronously clock out the received data on the RX on the
falling edge of the clock. Also known as RT or RXC.
In voice mode, the FCLK-RT pin delivers the 8 KHz framing clock
to the ADPCM codec.
Transceiver Signals
BSYNC-
OUT
7
O
Burst synchronization output. Burst synchronization pulse. Can be used
in a PBX environment, where several radios are co-located, to
synchronize the burst timing, thereby reducing "near end" interference.
Burst synchronization input. To be externally looped back to
BSYNC_OUT or to an external burst timing source.
Clock enable. When negated, disables the internal clock generator
circuit, thereby disabling the W9310 except for the OSCUP and the
SBI circuit.
Burst rate transmit data. Output of the TDD circuit to the transmitter
logic. It is the burst-rate baseband transmit signal prior to spreading
operation. Intended for use in testing only.
Burst rate receive data. Output of the receive module. It is the
burst-rate baseband receive clock. Intended for use in testing only.
Recovered clock. Output of the received clock from the receiver
module. It is the burst-rate receive clock. Intended for use in testing
only.
Remote lock. When asserted, RLOCK indicates that the acquisition
process has been completed. Refer to the operational section for
details.
Locked signal. When asserted, LOCKED indicates that initial
acquistion burst has been received. Refer to the operational section
for details.
Unique word detect. Active low signal that goes low whenever a
valid UW has been detected.
RF power switch. Designed to switch transmitter on when asserted
and off when de-asserted. Discussed in more detail in the
operational section.
Phase-locked loop switch. Design to switch the transceiver
synthesizer between TX and RX frequencies. It is asserted for TX
and de-asserted for RX. See operational section for details.
Transmitter enable. Designed to switch the antenna to the receiver
and to switch the receiver on when low. When asserted, connects
the antenna to the transmitter and switches the receiver off.
BSYNC_IN
8
I
CLKEN
51
I
TX_DATA
13
O
RCVDATA
14
O
RCVCLK
15
O
RLOCK
37
O
LOCKED
38
O
UWDET_N
39
O
RFPWR
67
O
PLLSW
73
O
TXEN
68
O
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