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參數(shù)資料
| 型號： | W9310 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Direct Sequence Spread Spectrum Transceiver(直接序列擴(kuò)展頻譜收發(fā)器) |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP80 |
| 封裝： | PLASTIC, QFP-80 |
| 文件頁數(shù)： | 17/36頁 |
| 文件大小： | 220K |
| 代理商： | W9310 |
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W9310
Publication Release Date: July 1996
- 17 -
Revision A3
the MHZ2_ST clock signal. Similarly, the W9310 delivers the received data to RX on the falling edge
of the FCLK_RT clock. This means that the RX data transition occurs on the falling edge of FCLK_RT
and the user should use the rising edge of the FCLK_RT clock signal to latch the RX data. Both
RTS_N and DCD_N transitions are synchronous with the appropriate clock edge (i.e., RTS_N
changes on the rising edge of MHZ2_ST and CTS_N changes on the falling edge of FCLK_RT). After
CTS_N assertion, the W9310 assumes that valid data will be available on the TX pin on the following
rising edge of the MHZ2_ST. For this reason, the user is advised to hold the TX pin at a binary "1"
prior to the first valid data bit. For the receive side, a special control pin, RXDELAY, can be used to
set the timing between the DCD_N assertion and valid RX output.
When RXDELAY is set to a binary "0" (default condition), the W9310 starts delivering valid received
data on the RX pin on the first falling edge after DCD_N assertion. When RXDELAY is set to a binary
"1," the W9310 delivers valid RX output on the eighth falling edge after DCD_N assertion. Prior to
valid RX output, the RX output is clamped at a binary "1."
The timing relationship between the data, clock, and handshaking signals is shown in Figure 5.
Detailed timing specifications are presented in the timing section. A typical start-up of the data link is
also shown in Figure 6; note that the same diagram would also apply for voice mode operation, with
the exception that the handshaking signals are not applicable and the relationship between the
MHZ2_ST and FCLK_RT timing is as shown in Figure 4 above.
MHZ2_ST
FCLK_RT
CTS_N
TX
DCD_N
RX
* Note: RTS_N and DTR_N are assumed to be already asserted.
Figure 5. Full-duplex Data Interface Timing
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