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參數資料
| 型號： | W9310 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 通信及網絡 |
| 英文描述： | Direct Sequence Spread Spectrum Transceiver(直接序列擴展頻譜收發器) |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP80 |
| 封裝： | PLASTIC, QFP-80 |
| 文件頁數： | 26/36頁 |
| 文件大小： | 220K |
| 代理商： | W9310 |
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W9310
- 26 -
M_BSYNC
M_TXEN
M_RFPWR
M_PLLSW
M_MODOUT
M-DI
S_TXEN
S_RFPWR
S_PLLSW
S_MODOUT
S_DI
0
259
768
19
20
371
370
787
788
-8
760
370
19
787
365
-14
-8
408
408
754
760
-14
408
754
19
787
365
-9
-9
381
409
759
759
Notes:
1. The timing is expressed as numbers of bits
2. The total number bits of per burst is fixed and equal for master and slave
3. The timing is assumed that there is no air propagation delay between master and slave
Test Circuits
The W9310 includes two multiplexers intended primarily for factory testing. The W9310 can be
placed in test mode by setting the TEST1 pin high and the CI0 bit high. In the test mode, the two
muxes, one 16
×
6 and the other 2
×
8, are used to observe the content of a set of registers. The 16
×
6 MUX is controlled by a 4-bit counter which can be incremented or decremented through the use of
XTRACLK clock and TC_UP (test counter up/down control) inputs. The 2
×
8 MUX is controlled by the
LSB bit of the test counter.
To reduce pin count, the test MUX pins are multiplexed with normal functional pins as shown in Table
2 and Table 3. For the 2
×
8 MUX, bit-directional buffers are used; during test mode, they are
configured as output pins, while during normal operation, they are configured as input pins. In the test
mode, the master oscillator can be frozen and the XTRACLK clock activated to scan the content of
internal storage elements. Alternatively, the master oscillator can run normally while the TESTCLK is
frozen so the output of the test muxes can be observed over time.
In addition to the XTRACLK, an additional test-only clock, X8KHZ, can be used to clock sub-modules
of the W9310 at a higher than normal clock rate (by bypassing the normal internal clock) during
testing.
Finally, two 7-bit bi-directional buses, EPX and EPY, are used for receiver testing. When set to output
mode, the two buses allow the correlator outputs to be observed. In the input mode, the correlators
are bypassed and external data can be applied through the EPX and EPY pins to test the remainder
of the receiver logic independent of the correlator.
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