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參數資料
| 型號： | W9310 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 通信及網絡 |
| 英文描述： | Direct Sequence Spread Spectrum Transceiver(直接序列擴展頻譜收發器) |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP80 |
| 封裝： | PLASTIC, QFP-80 |
| 文件頁數： | 16/36頁 |
| 文件大小： | 220K |
| 代理商： | W9310 |
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W9310
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and the FCLK_RT pin delivers the 8 KHz framing or sync clock to the ADPCM codec. The timing
diagram for the ADPCM interface is shown in Figure 4 below. Details concerning the timing
specifications are presented in the timing section.
MHZ2_ST
FCLK_RT
DATA
1
2
3
4
MSB
LSB
Figure 4. ADPCM Interface Timing
Data Mode Timing Information
When operating in the full-duplex data mode, the W9310 supports full-duplex data at rates up to 64
Kbps. For both voice and data mode full-duplex operation, it is necessary to lock the average rate of
writing data into the FIFOs to the average rate of reading data from the FIFOs. Since the number of
data bits per burst is fixed, as is the burst rate, this can be achieved by locking the sample clock onto
the burst rate.
For voice mode operation, the 8 Kframes/sec clock is locked onto the burst rate by a digital phase-
locked loop in the TDD control module. The phase-locked loop fine tunes the 8 Kframes/sec clock
delivered to the ADPCM codec, so that exactly 72 frame pulses are delivered per burst. During each
frame pulse, the ADPCM interface delivers and receives one nibble (4 bits) of data to and from the
ADPCM codec.
For data mode operation, an MO of 32.768 MHz is required for a full-duplex data rate of 64 Kbps.
Since the FIFOs are 8 bits wide, the framing clock for the 64 Kbps full-duplex data rate is 8
Kframes/sec. The PLL inside the TDD module adjusts the framing pulses so that exactly 36 frame
pulses are delivered per burst. During each frame pulse, the FIFO delivers and receives 1-byte of
data to an internal serial/parallel converter which receives and delivers the 1-bit serial data stream in
a continuous fashion.
In either data or voice mode operation, when no data are available, the W9310 delivers a continuous
binary "1" to the modulator and to the RX output.
For data mode, handshaking signals or modem control signals are fully implemented according to
RS-232C documentation. Specifically, the user must assert both ready-to-send (RTS_N) and data-
terminal-ready (DTR_N) signals before the W9310 will commence any data communication. Once
both RTS_N and DTR_N have been asserted, the W9310 starts communicating with the remote
W9310. After the preliminary acquisition process where the master and slave exchange acquisition
and empty bursts, the W9310 asserts a clear-to-send (CTS_N) signal to indicate to the user that the
W9310 is ready to accept data on the TX pin for transmission. Similarly, after the initial burst of actual
data transmission (after CTS_N has been asserted), a data-carrier detect (DCD_N) signal is asserted
to indicate to the user that valid data have been received and are available on the RX pin.
For synchronous communication, the W9310 provides the user both transmit and receive clock timing
on MNZ2_ST (Send Timing) and KHZ8-RT (Receive Timing). During data transmission, the W9310
samples the TX pin data on the rising edge of the MHZ2_ST. Consequently, the user should supply
the TX pin data in such a way that the transition data on the TX pin occur during the falling edge of
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