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參數資料
| 型號： | W9310 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 通信及網絡 |
| 英文描述： | Direct Sequence Spread Spectrum Transceiver(直接序列擴展頻譜收發器) |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP80 |
| 封裝： | PLASTIC, QFP-80 |
| 文件頁數： | 24/36頁 |
| 文件大?。?/td> | 220K |
| 代理商： | W9310 |
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W9310
- 24 -
Continued
1
1 bit
2
2 bits
3
3 bits
4
7
4 bits
CI12
LockSMon. Enables Locking State Machine when set to high (see Figure 2 for Locking State
Machine state diagram).
Test Bits
The test bits (5 bits) are used to internally program several multiplexers for use during testing. During
normal operation, they should be set to 0.
Reset and Disable Controls
The W9310 contains two clock enable and three reset control signals. The enable signals, OSCEN
and CLKEN, are used to enable the master clock oscillator and the internal clock generator,
respectively. When OSCEN is set to low, the on-chip clock oscillator will be disabled and
consequently the W9310 will be disabled also. When CLKEN is set low, the internal clock generator is
disabled, thus disabling most of the W9310's functions. However, the OSCUP clock output and the
SBI module are not affected by the CLKEN signal. This allows the SBI to function even when the
W9310 is disabled by the CLKEN signal. The three reset signals, ARST, RST1_N, and RST2_N, are
used to reset various parts of the W9310. When set to low, the ARST signal resets the
asynchronous/synchronous converter. In addition, when set to low, the ARST signal also disables the
ST8OUT clock. If the asynchronous/synchronous converter is not used, the ARST signal should be
set low so that the synchronous/synchronous converter is completely disabled and will not consume
any power. When set to low, the RST1_N reset signal resets storage elements in the W9310 and
disables all clocks except the master oscillator. The RST2_N reset signal resets the storage elements
and disables all clocks except those of the master oscillator and the SBI.
RF/IF Analog Interface
The W9310 interfaces with the RF/IF analog radio through the DI, MODOUT, PLLSW, and RFPWR
pins. DI is a CMOS-level input fed by the analog receiver. MODOUT is a tri-state output to the analog
transmitter. It is in high-impedance state when the W9310 is in the receive mode (TXEN is low).
PLLSW is used to switch the PLL of the analog radio and RFPWR is used to power the transmitter
power amplifiers on and off. The timing for PLLSW and that for RFPWR are shown in Figure 10 and
Figure 11, respectively. Note that the RFPWR timing is valid for both full-duplex and half-duplex
modes. The PLLSW timing shown is for the full-duplex mode; for half-duplex operation, the PLLSW
timing follows that of RFPWR. The BURST_CLK shown in Figure 10 is the burst rate clock, which is
2.667 times the data rate in full-duplex operation and is equal to the data rate in half-duplex
operation. For example, for a master oscillator of 16.384 MHz, the full-duplex burst rate is 85.333
KHz. Thus, the RFPWR signal will be asserted one burst clock cycle or 11.72
μ
sec after TXEN
assertion and will be de-asserted one burst clock cycle or 11.72
μ
S prior to TXEN de-assertion.
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